3D NAND Stair-Step Layout for Memory Access and Isolation
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Solution Overview
Problem
Current memory circuitry technologies face challenges in efficiently forming vertically-stacked memory cells with effective electrical access and isolation, particularly in three-dimensional NAND architectures, where the stair-step structure and conductive vias play a crucial role but require precise etching and material deposition processes to ensure proper functionality and scalability.
Innovation Solution
The integration of a stair-step region between two three-dimensional array regions, with alternating insulative and conductive tiers, where first and second stair-step structures with distinct tread configurations provide lateral electrical isolation and access, and methods involving 'gate-last' or 'replacement-gate' processing are employed to form these structures, enabling direct electrical coupling and efficient memory cell formation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If vertically-stacked memory cells are formed in three-dimensional NAND architecture, then memory density and capacity are improved, but manufacturing complexity and precision requirements increase
Solution Approach 1:
The memory array is divided into multiple memory blocks, each containing vertically-stacked memory cells. The stair-step structure segments the array into distinct regions with different depths, allowing independent formation and control of memory cells at different locations. This segmentation enables precise control over the three-dimensional structure while maintaining manufacturability.
Solution Approach 2:
The patent transitions from planar two-dimensional memory architecture to three-dimensional vertically-stacked architecture by introducing the stair-step structure with alternating insulative and conductive tiers. This dimensional change increases memory density by utilizing vertical space while the stair-step configuration provides necessary electrical isolation and access pathways.
2Reliability
If stair-step structure with alternating insulative and conductive tiers is implemented, then electrical isolation between memory cells is improved, but device complexity increases
Solution Approach 1:
The stair-step structure implements local quality by providing different structural configurations at different locations within the memory array. Each step region has tailored insulative and conductive tier arrangements optimized for specific electrical isolation and access requirements, rather than applying a uniform structure throughout the entire array.
Solution Approach 2:
The insulative tiers act as intermediary elements between adjacent conductive tiers and memory cell strings, providing electrical isolation while allowing controlled electrical access through conductive vias. This intermediary structure enables independent control of electrical connections to individual memory cells or groups of cells.
3Reliability
If gate-last or replacement-gate processing is used, then transistor performance and control are improved, but manufacturing process complexity increases
Solution Approach 1:
The gate-last and replacement-gate processing methods employ preliminary actions by first forming placeholder structures (such as sacrificial gates or temporary conductive layers) during the initial fabrication stages, then replacing or activating the actual gate structures later in the process. This allows other critical structures to be formed first with proper spacing and alignment, improving final transistor performance.
Data Source
AI summary
Integrated circuitry comprises two three-dimensional (3D) array regions individually comprising tiers of electronic components. A stair-step region is between the two 3D-array regions. First stair-step structures alternate with second stair-step structures along a first direction within the stair-step region. The first stair-step structures individually comprise two opposing first flights of stairs in a first vertical cross-section along the first direction. The stairs in the first flights each have multiple different-depth treads in a second vertical cross-section that is along a second direction that is orthogonal to the first direction. The second stair-step structures individually comprise two opposing second flights of stairs in the first vertical cross-section. The stairs in the second flights each have only a single one tread along the second direction. Other embodiments, including method, are disclosed.