3D NAND Staircase Beam Structure for Lower RC Delay

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

The 3D NAND flash memory faces challenges with increasing resistance and RC delay due to long connection lines and potential collapse of staircase structures as the number of stacking layers increases, affecting performance and fabrication complexity.

Innovation Solution

A memory device design with a stack structure featuring alternately arranged dielectric and electrode layers, including a staircase structure between array regions and discrete beam structures for mechanical support, and a bilateral word line-driving scheme to reduce resistance and prevent structure collapse.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If the number of stacking layers in the memory array structure increases, then the storage capacity increases, but the resistance of the connection lines increases causing RC delay

Engineering Contradiction:
Improvestorage capacityVSAvoidRC delay
Core Design Contradiction:
Quantity of substanceVSReliability

Solution Approach 1:

The patent transitions from planar 2D memory architecture to three-dimensional 3D NAND vertical stacking architecture. Memory cells are arranged in vertical columns extending through multiple stacked layers, enabling storage capacity to scale with the number of layers while maintaining acceptable connection line lengths through optimized vertical and lateral routing paths

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Reliability

If the staircase structure is disposed between two memory array structures to reduce connection line length, then the RC delay is reduced, but the wall structure height increases causing potential collapse

Engineering Contradiction:
ImproveRC delayVSAvoidwall structure stability
Core Design Contradiction:
ReliabilityVSStability of the object's composition

Solution Approach 1:

The continuous wall structure is segmented into multiple discrete support portions distributed at different vertical levels within the staircase structure. These segmented support portions provide mechanical reinforcement at critical intervals, preventing collapse of the overall wall structure while maintaining the bilateral connection architecture that reduces RC delay

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The wall structure is formed as a composite comprising multiple materials with different mechanical properties. The composite construction combines materials that provide both electrical insulation and mechanical strength, enabling the wall structure to withstand the increased heights required for bilateral staircase connections without collapsing

Inventive Principle:
Principle #40Composite materials

3Reliability

If electrical connections extend in both directions from the staircase structure to connect memory array structures, then the overall resistance decreases, but the fabrication complexity increases

Engineering Contradiction:
Improveoverall resistanceVSAvoidfabrication complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The staircase structure with bilateral connections serves multiple functions simultaneously: it provides mechanical support through the wall structure, establishes electrical connections in both directions to reduce resistance, and enables standardized fabrication processes. The same basic staircase and wall structure units are replicated throughout the device, providing universality that manages fabrication complexity despite the bilaterally connected architecture

Inventive Principle:
Principle #6Universality (Multi-functionality)

Data Source

PatentUS20250266354A1Memory device and fabrication method thereof
Publication Date: 2025.08.21 YANGTZE MEMORY TECH CO LTD
  • US20250266354A1 patent drawing
  • US20250266354A1 patent drawing
  • US20250266354A1 patent drawing

AI summary

A memory device includes a stack structure and a first beam structure. The memory device includes array regions and an intermediate region arranged between the array regions in a first lateral direction. The stack structure includes a first block and a second block arranged in a second lateral direction. Each of the first block and the second block includes a wall-structure region. In the intermediate region, the wall-structure regions of the first block and the second block are separated by a staircase structure. The first beam structure is located in the intermediate region and extends along the second lateral direction. The first beam structure is connected to the wall-structure regions of the first block and the second block. The first beam structure includes first dielectric layers and electrode layers that are alternately stacked.