3D NAND Staircase Stacks for Face-to-Face Logic Bonding
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Solution Overview
Problem
Existing memory technologies, such as DRAM, NAND, and MRAM, face limitations in terms of density, speed, and cost, making them inadequate for meeting the demands of modern applications.
Innovation Solution
A memory structure comprising a NAND block with a staircase structure of oxide layers, vias, bonding interconnects, and bitlines, which allows for face-to-face bonding with a logic wafer and enables efficient stacking of memory layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If traditional memory structures (DRAM, NAND, MRAM) are used, then each technology has its own advantages, but they all suffer from limitations in density, speed, or cost that make them inadequate for modern applications
Solution Approach 1:
The patent transitions from planar memory structures to three-dimensional stacked architecture. Multiple memory layers are stacked vertically with bonding interconnects connecting corresponding elements across layers. This vertical stacking enables significantly higher storage density while maintaining access speed by keeping all layers accessible through the stacking architecture.
Solution Approach 2:
The patent implements a nested structure where memory cells are formed within tunnel oxides that are themselves nested within stacked memory layers. Each layer contains complete memory functionality (tunnel oxide, charge trap layer, blocking oxide, electrodes) nested within the three-dimensional stack, creating a compact hierarchical structure that maximizes density.
2Quantity of substance
If memory density is increased using vertical stacking, then storage capacity improves, but manufacturing precision requirements increase due to the need for accurate alignment of vias and bonding interconnects across multiple layers
Solution Approach 1:
The patent forms via structures and bonding interconnect patterns in each memory layer before stacking. The bonding interconnects are prepared in advance with precise patterns that will align with corresponding structures in adjacent layers. This preliminary preparation of connection structures enables accurate alignment during the stacking process without requiring post-stack adjustment.
Solution Approach 2:
The patent employs different structural configurations at different locations within the memory device. Bonding interconnects are positioned at specific locations (e.g., at corners or edges of the stack) rather than uniformly distributed, allowing for localized precision requirements. The staircase structure of oxide layers creates different local geometries that facilitate alignment at specific regions while maintaining overall manufacturing feasibility.
3Adaptability or versatility
If complex bonding structures are used to achieve face-to-face bonding with logic wafers, then integration capability improves, but device complexity and manufacturing difficulty increase
Solution Approach 1:
The bonding interconnects serve multiple functions: they provide electrical connection between memory layers, serve as alignment features during stacking, and enable face-to-face bonding with logic wafers. This multi-functionality reduces the need for separate dedicated bonding structures, simplifying the overall manufacturing process while maintaining high integration capability.
Solution Approach 2:
The patent divides the bonding interface into multiple discrete bonding interconnect elements distributed across the memory stack. Rather than requiring a single complex bonding structure, the segmentation into multiple simpler interconnect elements allows for modular manufacturing and reduces the complexity of each individual bonding operation while achieving comprehensive integration with logic wafers.
Data Source
AI summary
A memory structure is provided, including a NAND block comprising a plurality of oxide layers, the plurality of layers forming a staircase structure at a first edge of the NAND block, a plurality of vias disposed on the staircase structure of NAND block, two or more of plurality of vias terminating along a same plane, a plurality of first bonding interconnects disposed on the plurality of vias, a plurality of bitlines extending across the NAND block, and a plurality of second bonding interconnects disposed along the bitlines. The memory structure may be stacked on another of the memory structure to form a stacked memory device.