3D NAND Staircase Dielectric Doping for Larger Word Line Contacts
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Solution Overview
Problem
The challenge in fabricating 3D-NAND memory devices is to increase the landing window of word line contacts without compromising the manufacturing process, as the existing methods require precise control over the selective formation of SiN layers, which adds complexity and difficulty to subsequent processes.
Innovation Solution
The solution involves doping SiN layers with elements such as carbon, phosphorus, boron, arsenic, and oxygen to reduce their etch rate, allowing them to function as etch stop layers and prevent word line contacts from punching through the word line layers at the steps of the staircase region.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If SiN layers are formed with precise selective control, then the landing window of word line contacts can be increased, but the manufacturing process complexity and difficulty increase
Solution Approach 1:
The patent changes the etch rate parameter of the SiN layer by doping it with carbon, phosphorus, boron, arsenic, or oxygen. This parameter change allows the SiN layer to serve as an etch stop layer with controlled etch resistance, enabling precise control of the word line contact formation without requiring complex selective formation processes. The doped SiN layer has different etch characteristics compared to undoped SiN, allowing it to stop the etching process at the desired location and prevent word line contacts from punching through the word line layers.
2Reliability
If SiN layers are doped to reduce etch rate, then word line contacts are prevented from punching through, but the doping process adds manufacturing steps
Solution Approach 1:
The patent merges the SiN layer formation with the doping process by incorporating dopant elements during the deposition step. This combining of functions allows the SiN layer to simultaneously serve as a structural layer and an etch stop layer with controlled etch resistance, eliminating the need for separate doping steps and reducing overall manufacturing complexity.
Solution Approach 2:
By changing the chemical composition parameter of the SiN layer through doping, the patent achieves controlled etch resistance that prevents word line contacts from punching through. The doping process modifies the physical and chemical properties of the SiN layer, making it resistant to etching while maintaining its structural function.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach simplifies the manufacturing process by allowing for easier control of the formation of staircase regions in 3D-NAND memory devices, thereby increasing the landing window of word line contacts and preventing them from punching through the word line layers.
Implementation Method 1
The dielectric layer can be doped with one or a combination of carbon, phosphorous, boron, arsenic, and oxygen
Data Source
AI summary
In a method for fabricating a semiconductor device, a stack of alternating insulating layers and sacrificial layers are formed over a substrate. A staircase having a plurality of steps are formed in the stack. Each of the steps has a tread and a riser and further includes a respective pair of the insulating layer and the sacrificial layer over the insulating layer of the respective step. A dielectric layer is formed along the treads and risers of the steps and is doped with one or a combination of carbon, phosphorous, boron, arsenic, and oxygen. The sacrificial layers are further replaced with a conductive material to form word line layers that are arranged between the insulating layers. A plurality of word line contacts are formed to extend from the word line layers of the plurality of steps, and further extend through the dielectric layer.