3D NAND Staircase Gate Structure for Capacity and Stability
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Solution Overview
Problem
Current semiconductor devices face challenges in increasing data storage capacity and ensuring reliability, particularly in three-dimensional memory cell arrangements.
Innovation Solution
The semiconductor device incorporates a unique staircase structure with stacked and spaced gate electrodes, channel structures, support structures, and contact structures to enhance data storage capacity and reliability, featuring a substrate with vertically stacked gate electrodes and channel layers, and support structures that provide stability and connectivity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory cells are arranged three-dimensionally to increase data storage capacity, then data storage capacity is improved, but structural stability deteriorates
Solution Approach 1:
The patent transitions from two-dimensional memory cell arrangement to three-dimensional arrangement by stacking gate electrodes vertically and extending them in staircase form horizontally. This multi-dimensional configuration increases data storage capacity while maintaining structural integrity through carefully designed support structures that stabilize the three-dimensional architecture.
Solution Approach 2:
The gate electrodes are divided into multiple stacked layers (first gate electrodes and second gate electrodes) that are spaced apart vertically. This segmentation allows for increased storage capacity through vertical stacking while each layer can be independently supported, thereby maintaining structural stability throughout the three-dimensional structure.
2Quantity of substance
If gate electrodes are stacked vertically to increase storage capacity, then data storage capacity is improved, but manufacturing complexity increases
Solution Approach 1:
The patent employs preliminary patterning actions where mandrels are formed first, followed by sequential deposition of insulating layers and gate electrode layers. Each layer is prepared and patterned before the next is added, which simplifies the manufacturing process compared to attempting to create the entire three-dimensional structure in a single step.
Solution Approach 2:
The structure is built through nested layering where first gate electrodes are stacked, then second gate electrodes are stacked on top. Each layer is nested within the overall three-dimensional structure, allowing for systematic manufacturing through repeated deposition and patterning cycles rather than complex single-step processes.
3Reliability
If support structures are added to maintain structural stability, then reliability is improved, but device complexity increases
Solution Approach 1:
The support structures serve multiple functions: they maintain structural stability of the three-dimensional arrangement, provide mechanical support for vertically stacked gate electrodes, and enable the staircase extension configuration. By consolidating these functions into a single structural element, the patent improves reliability without proportionally increasing complexity.
Solution Approach 2:
The support structures act as intermediaries between the vertically stacked gate electrodes and the substrate. They provide the necessary mechanical support and spacing, allowing the gate electrodes to maintain their vertical arrangement while being anchored to the substrate, thereby simplifying the overall structural design compared to direct electrode-substrate connections.
Data Source
AI summary
A semiconductor device includes first and second gate electrodes stacked and spaced apart from each other in a first direction on a first region of a substrate, and extending in staircase form in a second direction on a second region of the substrate, the second gate electrodes disposed on the first gate electrodes; a first support structure penetrating the first gate electrodes on the second region, extending in the first direction, and having an upper end disposed at a level lower than a level of a lowermost second gate electrode among the second gate electrodes; a second support structure penetrating at least one of the first and second gate electrodes on the second region, extending in the first direction, and having an upper end disposed at a level higher than a level of un uppermost second gate electrode among the second gate electrodes.