3D NAND Staircase Layout to Reduce Trim-Etch Complexity
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Solution Overview
Problem
The existing trim-etch process for forming stair steps in 3D NAND memory devices is inefficient, requiring thicker mask layers for large height differences, leading to difficulties in lithography and high costs, and can be improved by reducing the number of trim-etch cycles and height differences.
Innovation Solution
The semiconductor device employs a multi-level staircase architecture with divided stack sections, using a chop process to reduce the number of trim-etch cycles and height differences, and forms stair steps in different sections simultaneously, followed by a chop process to shift stair steps to appropriate layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If the existing trim-etch process is used to form stair steps with large height differences, then the stair steps can be formed, but thicker mask layers are required leading to difficulties in lithography and high costs
Solution Approach 1:
The patent divides the stack into multiple sections and forms stair steps in different sections simultaneously. By segmenting the stair step formation process across multiple sections, the height difference that each trim-etch cycle needs to handle is reduced, eliminating the need for excessively thick mask layers and simplifying lithography requirements.
Solution Approach 2:
The patent introduces a sectional dimension to the stair step formation process. Instead of forming all stair steps in a single sequence, it distributes stair step formation across multiple sections along the vertical axis, allowing parallel processing and reducing the height difference burden on individual trim-etch cycles.
2Manufacturing precision
If the existing trim-etch process is used for forming stair steps, then stair steps can be formed, but the number of trim-etch cycles increases leading to reduced processing efficiency
Solution Approach 1:
The patent segments the stack into multiple sections and forms stair steps in different sections simultaneously through parallel trim-etch processes. This segmentation allows multiple stair steps to be formed in fewer cycles compared to sequential formation, significantly improving processing efficiency.
Solution Approach 2:
The patent merges the stair step formation processes of multiple sections into simultaneous operations. By combining the formation of stair steps across different sections into parallel trim-etch cycles, the total number of processing cycles is reduced, enhancing productivity.
3Manufacturing precision
If the existing trim-etch process is used with large height differences, then stair steps can be formed, but the complexity of the trim-etch process increases
Solution Approach 1:
The patent segments the overall stair step formation into multiple smaller tasks distributed across different sections. Each section handles a manageable height difference, simplifying the trim-etch process parameters and reducing process complexity compared to forming all stair steps in a single high-height-difference operation.
Solution Approach 2:
The patent adds a sectional dimension to the trim-etch process, distributing the formation workload across multiple sections. This dimensional distribution reduces the height difference burden on each trim-etch cycle, simplifying process control and reducing overall process complexity.
Data Source
AI summary
A semiconductor device includes a stack including gate layers and insulating layers alternately stacked along a first direction, channel structures located in an array region of the stack, a first staircase located at a first section in a connection region of the stack, the connection region and the array region arranged in a second direction perpendicular to the first direction, a second staircase located at a second section in the connection region of the stack, and an intermediate staircase located at the first section and disposed between the first staircase and the second staircase in the second direction. The intermediate staircase includes intermediate group stair steps ascending in the second direction. The intermediate staircase has a first sidewall and a second sidewall in the second direction. The second sidewall is closer to the second staircase than the first sidewall. The second sidewall is parallel to the first direction. The intermediate group stair steps of the intermediate staircase face the first staircase.