3D NAND Multi-Stack Staircase Patterning for Pillar Alignment
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Solution Overview
Problem
The fabrication processes of multiple-stack 3D NAND memory devices are time-consuming and costly due to the need for multiple photomasks and high precision etching, which can affect film quality and uniformity, and result in unaligned sidewalls of supporting pillars.
Innovation Solution
A single staircase-forming patterning process is used to pattern dielectric pairs of multiple stacks, allowing pillar holes to be formed after the formation of the multiple-stack staircase structure, reducing the number of photomasks and improving sidewall alignment.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If multiple photomasks and high precision etching are used to form supporting pillars, then the alignment and uniformity of sidewalls can be improved, but the fabrication process becomes time-consuming and costly
Solution Approach 1:
The patent combines the formation of supporting pillars and channel holes into a single etching process. By using a unified patterning approach where the same photoresist layer defines both pillar locations and channel hole locations, multiple structures are created simultaneously rather than through separate sequential steps, thereby reducing fabrication time while maintaining alignment precision
Solution Approach 2:
The supporting pillars serve multiple functions: they provide mechanical support during fabrication, define channel hole positions through their spacing, and act as spacers. This multi-functionality eliminates the need for dedicated separate structures or processes, simplifying the overall fabrication approach
2Manufacturing precision
If multiple photomasks are used to pattern dielectric pairs, then the manufacturing precision can be improved, but the fabrication cost and complexity increase
Solution Approach 1:
The patent merges multiple patterning steps into a single patterning operation. By designing the photoresist pattern to simultaneously define supporting pillars, channel holes, and dielectric pair boundaries in one exposure and development step, the need for multiple photomasks is eliminated, reducing both cost and process complexity
Solution Approach 2:
The photoresist layer is applied and patterned before any etching or material deposition steps. This preliminary patterning action establishes all subsequent feature locations (pillars, channels, dielectrics) in advance, allowing all these structures to be formed with reference to the same pattern template, ensuring alignment without requiring additional photomasks
3Stability of the object's composition
If supporting pillars are formed before channel holes, then mechanical support is provided during fabrication, but the fabrication process becomes more time-consuming
Solution Approach 1:
The patent performs the etching of supporting pillars and channel holes in the same process step using a single photoresist mask. The photoresist pattern simultaneously exposes locations for both pillars and channels, and the etching process creates both structures concurrently, providing mechanical support during fabrication while maintaining high productivity
Solution Approach 2:
The supporting pillars automatically provide mechanical support during the etching process because they are formed as part of the same structure being etched. The pillars and channels are created together from the same dielectric stack, so the pillars inherently support the overlying structures during fabrication without requiring separate support mechanisms
Data Source
AI summary
In an example, a memory device includes a first stack structure and a second stack structure over the first stack structure. Each of the first stack structure and the second stack structure includes alternately stacked conductor layers and first insulating layers. The memory device also includes a first channel structure extending through the first stack structure, and a second channel structure extending through the second stack structure and connected with the first channel structure. A width of an end of the first channel structure closer to the second channel structure is greater than that of the second channel structure closer to the first channel structure. The memory device further includes a pillar structure extending through the first stack structure and the second stack structure. The pillar structure includes a metal layer.