3D NAND Interconnect Staircase Structure for Vertical Routing
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Solution Overview
Problem
Planar memory cell technologies face challenges in scaling due to limitations in feature size and fabrication costs, necessitating a transition to 3D memory architectures to enhance memory density.
Innovation Solution
A 3D NAND memory device is developed with a substrate, alternating layer stacks, and interconnect structures, including a staircase structure, barrier layers, and slit structures, which allow for vertical interconnects and reduced process complexity and cost through the formation of alternating dielectric and conductor layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If planar memory cell scaling is continued, then memory density increases, but feature size approaches lower limit and fabrication becomes challenging and costly
Solution Approach 1:
The patent transitions from planar (2D) memory cell architecture to three-dimensional (3D) memory architecture by stacking multiple memory layers vertically. This dimensional change allows continued memory density improvement without further reducing lateral feature sizes, thereby avoiding the manufacturing precision challenges and costs associated with sub-limitscale planar features.
2Quantity of substance
If planar memory cell scaling is continued, then memory density increases, but fabrication cost increases
Solution Approach 1:
By moving to 3D stacked architecture, the patent achieves higher memory density through vertical stacking rather than lateral scaling. This approach uses more成熟 and cost-effective fabrication processes for larger feature sizes, thereby reducing the escalating fabrication costs associated with continuing planar scaling to sub-limitscale dimensions.
3Quantity of substance
If 3D memory architecture is implemented, then memory density increases and fabrication cost decreases, but interconnect structure complexity increases
Solution Approach 1:
The patent segments the interconnect structure into alternating conductor and dielectric layers forming a stacked configuration. This segmentation allows independent formation and control of each interconnect layer, simplifying the overall complex interconnect architecture while enabling efficient vertical and lateral connections in the 3D memory device.
Solution Approach 2:
The alternating conductor/dielectric stack serves multiple functions: providing vertical interconnects between memory layers, serving as word line and bit line structures, and enabling both lateral and vertical signal routing. This multi-functionality reduces the need for separate dedicated interconnect structures, thereby managing complexity.
Data Source
AI summary
Embodiments of interconnect structures of a three-dimensional (3D) memory device and method for forming the interconnect structures are disclosed. In an example, a 3D NAND memory device includes a substrate, an alternating layer stack including a staircase structure on the substrate, and a barrier structure extending vertically through the alternating layer stack. The alternating layer stack includes an alternating dielectric stack and an alternating conductor/dielectric stack. The alternating dielectric stack includes dielectric layer pairs enclosed by at least the barrier structure. The alternating conductor/dielectric stack includes conductor/dielectric layer pairs. The memory device further includes a channel structure and a slit structure each extending vertically through the alternating conductor/dielectric stack, an etch stop layer on an end of the channel structure, and first contacts. Each of a conductor layer of the alternating conductor/dielectric stack in the staircase structure, the etch stop layer, and the slit structure is in contact with one of the first contacts.