3D NAND Staircase Supporting Structure for SEG Stack Stability
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Solution Overview
Problem
In 3D NAND memory devices, the formation of sidewall selective epitaxial growth (SEG) is complicated by the need to avoid etching of memory films and semiconductor channels, leading to issues like leakage current, parasitic capacitance, and stack structure collapse in the staircase region due to the use of continuous sacrificial layers.
Innovation Solution
A supporting structure is introduced that overlaps the staircase region, replacing part of the sacrificial layer to prevent collapse and enhance yield by using a material different from the sacrificial layer, thereby sustaining the stack structure during SEG formation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a continuous sacrificial layer is used in 3D NAND memory devices, then the sidewall selective epitaxial growth process becomes complicated, but the stack structure lacks support leading to collapse in the staircase region
Solution Approach 1:
The continuous sacrificial layer is divided into two distinct portions: a supporting portion that remains in the staircase region to maintain structural integrity, and a sacrificial portion that is removed to enable SEG formation. This segmentation resolves the contradiction by allowing the supporting portion to prevent collapse while the sacrificial portion enables the SEG process without requiring complex continuous layer management.
Solution Approach 2:
The block plug serves as an intermediary structure that divides the sacrificial layer into supporting and sacrificial portions. It provides mechanical support during processing and enables selective removal of the sacrificial portion while retaining the supporting portion, thus resolving the conflict between structural stability and process complexity.
2Ease of manufacture
If the sacrificial layer is removed completely, then SEG formation is simplified, but the stack structure collapses in the staircase region
Solution Approach 1:
By segmenting the sacrificial layer into supporting and sacrificial portions, the solution allows complete removal of the sacrificial portion to simplify SEG formation, while the supporting portion remains to prevent stack collapse. This resolves the contradiction between ease of manufacture and structural integrity.
Solution Approach 2:
Different regions of the former sacrificial layer location have different qualities: the supporting portion retains material to provide local structural support in the staircase region, while the sacrificial portion is completely removed to facilitate SEG. This local differentiation resolves the contradiction between simplifying SEG and maintaining integrity.
3Reliability
If a supporting structure is introduced to prevent collapse, then stack structure integrity is maintained, but the device structure becomes more complex
Solution Approach 1:
The supporting structure function is merged with the existing sacrificial layer by retaining a supporting portion of it, rather than introducing a completely separate structure. This combines the support function with the existing layer architecture, reducing overall structural complexity while maintaining integrity.
Solution Approach 2:
The supporting portion of the sacrificial layer serves multiple functions: it provides structural support to prevent collapse, maintains alignment during processing, and eliminates the need for separate supporting structures. This multi-functionality reduces device complexity while ensuring reliability.
Data Source
AI summary
A three-dimensional (3D) memory device includes a core array region and a staircase region adjacent to the core array region. The core array region includes a memory stack having a plurality of conductor layers and a plurality of dielectric layers stacked alternatingly, a first semiconductor layer disposed over the memory stack, and a channel structure extending through the memory stack and the first semiconductor layer. The staircase region includes a staircase structure, a supporting structure disposed over the staircase structure, and a plurality of contacts contacting the plurality of conductor layers in the staircase structure. The first semiconductor layer overlaps the core array region in a plan view of the 3D memory device and the supporting structure overlaps the staircase region in the plan view of the 3D memory device.