3D NAND Staircase Layout for Fewer Trim-Etch Cycles
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Solution Overview
Problem
The existing trim-etch process for forming stair steps in 3D NAND flash memory devices is inefficient due to high cost, low productivity, and difficulties in lithography caused by large height differences between stair steps, requiring thicker mask layers which complicate the process.
Innovation Solution
The semiconductor device employs a multi-level staircase architecture with sections divided into groups and divisions, allowing for reduced trim-etch cycles and height differences, thereby improving processing efficiency through the use of a chop process to shift stair steps and reduce the number of trim-etch cycles.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If traditional trim-etch process is used to form stair steps, then stair steps can be formed, but the process is inefficient with high cost and low productivity due to large height differences requiring thicker mask layers
Solution Approach 1:
The connection region is divided into multiple sections (first section, second section, etc.), and each section is further divided into groups and divisions. This segmentation allows the trim-etch process to be performed in smaller, more manageable cycles, reducing the height differences that need to be addressed in each individual cycle and thereby improving productivity and reducing process complexity.
Solution Approach 2:
The chop process is used to pre-shift the stair steps to their final positions before the trim-etch process. This preliminary action reduces the height differences that the trim-etch process must accommodate, allowing for thinner mask layers and fewer trim-etch cycles, thus improving processing efficiency and reducing cost.
2Manufacturing precision
If larger height differences between stair steps are accommodated, then more comprehensive contact formation is achieved, but thicker mask layers are required which complicate the lithography process
Solution Approach 1:
The chop process performs a preliminary shift of stair steps to their target positions before the trim-etch process. This preliminary action significantly reduces the height differences that subsequent trim-etch cycles must address, enabling the use of thinner mask layers that are easier to handle in lithography while still achieving precise contact formation.
Solution Approach 2:
By dividing the connection region into multiple sections with progressively smaller height differences, each trim-etch cycle operates on reduced height variations. This segmentation enables the use of thinner, more manageable mask layers for each individual trim-etch cycle while maintaining overall manufacturing precision through the cumulative effect of multiple precise steps.
3Manufacturing precision
If more trim-etch cycles are performed, then more precise stair steps are achieved, but processing time and cost increase
Solution Approach 1:
The chop process performs the bulk of the stair step positioning in advance, before the trim-etch cycles begin. This preliminary action eliminates the need for numerous trim-etch cycles to achieve the required precision, as the height differences remaining after the chop process are small and can be corrected with fewer, more efficient trim-etch cycles.
Solution Approach 2:
The division of the connection region into multiple sections with progressively refined height differences allows trim-etch cycles to be performed on smaller, more manageable increments. This segmentation means that each trim-etch cycle achieves its precision goal more efficiently, reducing the total number of cycles required compared to processing the entire height difference in a single或少量 cycles.
Data Source
AI summary
In a semiconductor device, a stack of alternating gate layers and insulating layers is formed. Channel structures are formed in an array region of the stack. A first staircase is formed at a first section of the stack. A second staircase is formed at a second section of the stack. A dummy staircase is formed at the first section and disposed between the first staircase and the second staircase. The dummy staircase includes dummy group stair steps descending in a second direction parallel to a plane defined by any one of the gate layers and the insulating layers, and dummy division stair steps descending in a third direction and a fourth direction parallel to the plane and perpendicular to the second direction. The third direction and the fourth direction are opposite to each other.