3D NAND Programming with State Grouping for Faster Writes
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Solution Overview
Problem
As memory devices shrink to smaller die sizes to reduce manufacturing costs and increase storage density, scaling of planar memory cells faces challenges due to process technology limitations and reliability issues, particularly in 3D NAND memory devices where increasing the number of bits stored in each cell leads to longer programming times and reduced read margins.
Innovation Solution
A method for programming memory cells involves grouping adjacent target programmed states based on coupling offsets and performing multiple verification operations using different verification voltages to efficiently program and read memory cells, including a first program operation followed by a second verification operation to achieve precise programming states.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the number of bits stored in each memory cell is increased to increase storage density, then storage capacity is improved, but programming time increases
Solution Approach 1:
The programming process is divided into two distinct passes: a first pass that programs memory cells to intermediate states, and a second pass that programs them to final target states. This segmentation allows the system to handle multi-bit cells more efficiently by breaking down the complex programming task into manageable stages, reducing overall programming time while maintaining high storage capacity.
Solution Approach 2:
The first pass performs preliminary programming of memory cells to intermediate states before the second pass programs them to final target states. This preliminary action prepares the memory cells in advance, making the subsequent programming operation more efficient and reducing the total time required for multi-bit programming.
2Quantity of substance
If the number of bits stored in each memory cell is increased to increase storage density, then storage capacity is improved, but read margin is reduced
Solution Approach 1:
By dividing the programming process into two passes with distinct verification steps, the system can more precisely control and verify the programming of each bit. The first verification operation checks intermediate states while the second verification operation checks final states, improving read margin through staged verification.
Solution Approach 2:
The patent implements verification operations after each programming pass, creating feedback loops that allow the system to check and adjust programming accuracy. The first verification operation provides feedback on intermediate states, and the second verification operation provides feedback on final states, ensuring adequate read margins are maintained even as storage capacity increases.
3Manufacturing precision
If verification operations are performed after each programming pass to improve programming accuracy, then programming precision is improved, but processing time is increased
Solution Approach 1:
The verification process is segmented into two separate operations corresponding to the two programming passes. Rather than performing a single comprehensive verification, the system performs targeted verification at each stage, which reduces the total verification time while maintaining high programming precision through staged checking.
Solution Approach 2:
The first verification operation performs preliminary checking of intermediate programming states, catching errors early before the second programming pass. This preliminary verification prevents compounding errors and reduces the need for re-programming, ultimately saving time despite the additional verification step.
Data Source
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AI summary
The present disclosure provides a programming method, a memory device and a memory system. The method includes, based on coupling offsets, dividing target programmed states into N groups, each group corresponding to a different first programmed state, wherein an i-th group has Ki number of different target programmed states and corresponds to an i-th first programmed state. At least two groups of target programmed states have two different numbers of target programmed states. The method also includes performing a first program operation to program memory cells to respective first programmed states; and performing a second program operation to program an i-th group of memory cells at the i-th first programmed state to Ki number of different target programmed states.