3D NAND Memory Structure With String Cut Insulation Protrusions
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Solution Overview
Problem
Current semiconductor memory devices face challenges in achieving high integration density and reliable electrical characteristics, particularly in multifunctional information and communication devices that require large capacity and high integration.
Innovation Solution
The semiconductor memory device incorporates a plurality of gate electrodes arranged on a substrate with insulation layers in between, featuring channel structures with a circular cross-section and string selection line cut insulation layers that separate the upper insulation layer from the gate electrodes, enhancing integration and reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If conventional memory device structures are used, then manufacturing is simpler, but integration density and storage capacity are limited
Solution Approach 1:
The patent transitions from planar 2D memory structures to vertical 3D structures by stacking multiple gate electrodes, insulation layers, and channel structures in the depth direction. This dimensional change enables significantly higher integration density and storage capacity within the same footprint area.
Solution Approach 2:
The patent implements nested structures where channel structures are positioned within recesses formed in the substrate, and multiple functional layers (gate electrodes, insulation layers, barrier layers) are stacked concentrically and sequentially. This nesting approach maximizes space utilization and achieves high density.
2Quantity of substance
If integration density is increased, then storage capacity improves, but electrical characteristics and reliability may deteriorate
Solution Approach 1:
The patent applies different materials and structures to different regions: barrier layers with specific work functions are placed at gate-electrode/channel interfaces to control carrier injection, different insulation materials are used in different layers for electrical isolation, and doped regions are selectively positioned to optimize electrical characteristics while maintaining high density.
Solution Approach 2:
The patent employs composite structures combining multiple materials with complementary properties: gate electrodes use conductive materials, insulation layers use dielectric materials, barrier layers use materials with appropriate work functions, and channel structures use semiconducting materials. This composite approach ensures both high integration density and reliable electrical characteristics.
3Area of stationary object
If vertical stacking is implemented to increase integration, then area utilization improves, but manufacturing precision requirements increase
Solution Approach 1:
The patent divides the vertical stack into discrete, separable layers (gate electrodes, insulation layers, channel structures, barrier layers) that can be formed and positioned independently through sequential manufacturing steps. This segmentation allows for better control of each layer's dimensions and position, reducing cumulative alignment errors.
Solution Approach 2:
The patent forms preliminary structures such as recesses in the substrate, sacrificial layers, and template patterns before depositing subsequent layers. These preliminary structures serve as guides and constraints that automatically position subsequent layers with high precision, reducing the need for complex alignment procedures.
Data Source
AI summary
A semiconductor memory device includes gate electrodes arranged on a substrate to be spaced apart from each other in a first direction perpendicular to an upper surface of the substrate, an upper insulation layer arranged on an uppermost gate electrode, channel structures penetrating through the upper insulation layer, and the gate electrodes in the first direction, and string selection line cut insulation layers horizontally separating the upper insulation layer and the uppermost gate electrode. Each of the string selection line cut insulation layers includes a protrusion protruding toward the uppermost gate electrode and positioning on the same level as the first gate electrode.