3D NAND Flash Memory String Offset and Shielding Voltage

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

In high-density 3D NAND flash memory devices, the coupling effect between neighboring vertical channel NAND strings causes program disturb during simultaneous programming, leading to inefficiencies and errors in data storage.

Innovation Solution

The memory device employs a controller to execute specific voltage application sequences across multiple NAND strings, using shielding and program voltages to mitigate coupling effects by offsetting strings and applying voltages in a particular pattern to reduce string level jumps and weak boosts, thereby maintaining consistent programming operations.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If memory cells in neighboring NAND strings are programmed at the same time, then programming productivity is improved, but coupling effect between NAND strings causes program disturb

Engineering Contradiction:
Improveprogramming speedVSAvoidprogram disturb
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The array of NAND strings is divided into first and second pluralities of strings, disposed on opposite vertical sides of word lines. This segmentation allows independent programming control of each plurality, enabling selective programming that avoids simultaneous programming of neighboring strings and thus prevents coupling effects while maintaining productivity.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Different programming operations are applied to different regions of the array. The first program operation programs memory cells in the first plurality of strings, while the second program operation programs memory cells in the second plurality of strings. This localized programming approach ensures that neighboring strings are not programmed simultaneously, eliminating coupling effects while maintaining overall programming efficiency.

Inventive Principle:
Principle #3Local quality

2Quantity of substance

If high density array of vertical channel NAND strings is used, then storage capacity is improved, but coupling effect between neighboring strings increases

Engineering Contradiction:
Improvestorage capacityVSAvoidcoupling effect
Core Design Contradiction:
Quantity of substanceVSObject-affected harmful factors

Solution Approach 1:

The NAND strings are arranged with asymmetric positioning relative to word lines. The first plurality of strings is disposed on first vertical sides of word lines, while the second plurality of strings is disposed on second vertical sides. This asymmetric arrangement creates spatial separation that reduces coupling effects between neighboring strings in high-density configurations.

Inventive Principle:
Principle #4Asymmetry

Solution Approach 2:

The patent utilizes vertical stacking of word lines to create a three-dimensional arrangement. Memory cells are disposed at intersections of NAND strings and word lines in multiple stacks, effectively using the vertical dimension to increase storage capacity while maintaining horizontal spacing between string groups to reduce coupling effects.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

3Reliability

If shielding voltage is applied to reduce coupling effect, then program disturb is reduced, but programming operation complexity increases

Engineering Contradiction:
Improveprogram disturbVSAvoidprogramming operation
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent applies shielding voltage to specific strings before programming adjacent strings. By preemptively applying shielding voltage to strings that will not be programmed in the current operation, the coupling effect is prevented before it can cause program disturb, eliminating the need for complex real-time voltage adjustments during programming.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS20190295652A1Program scheme in 3D NAND flash memory
Publication Date: 2019.09.26 MACRONIX INTERNATIONAL CO LTD
  • US20190295652A1 patent drawing
  • US20190295652A1 patent drawing
  • US20190295652A1 patent drawing

AI summary

A memory device comprises a plurality of stacks of word lines, the word lines in the stacks having first vertical sides and second vertical sides opposite the first vertical sides, and a first plurality of strings and a second plurality of strings disposed respectively on the first vertical sides and the second vertical sides of the word lines in a particular stack in the plurality of stacks. The second plurality of strings is offset from the first plurality of strings in a direction along which the word lines in the particular stack extend. A first program operation includes applying a shielding voltage to a first string in the first plurality of strings and a fourth string in the second plurality of strings, and applying a program voltage to a second string in the second plurality of strings and a third string in the first plurality of strings.