3D NAND Sub-Block Select Gates for Lower Parasitic Coupling
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Solution Overview
Problem
As 3D-NAND memory devices migrate to higher capacity with increasing block size, the shared bottom select gate (BSG) leads to longer erasing and data transfer times and lower storage efficiency due to increased parasitic capacitance and coupling effects.
Innovation Solution
The 3D-NAND memory device is designed with a divided block structure, where the shared BSG is separated into sub-BSGs through dielectric trenches, allowing individual control of each sub-block, and the shared top select gate (TSG) is similarly divided into sub-TSGs, reducing parasitic capacitance and enabling independent operation of sub-blocks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the block size is increased to achieve higher storage capacity, then the storage capacity is improved, but the erasing time and data transfer time increase
Solution Approach 1:
The patent divides the memory device into multiple independent blocks, where each block has its own dedicated bottom select gate (BSG) and top select gate (TSG). This segmentation allows parallel operation of multiple blocks, enabling simultaneous erasing and data transfer operations across different blocks, thereby reducing the overall time required for these operations while maintaining high storage capacity.
2Quantity of substance
If the block size is increased to achieve higher storage capacity, then the storage capacity is improved, but the storage efficiency decreases
Solution Approach 1:
The patent divides the memory device into multiple independent blocks with dedicated select gates, enabling parallel access to different blocks. This segmentation improves storage efficiency by allowing simultaneous read, program, and erase operations across multiple blocks, thereby increasing productivity without sacrificing storage capacity.
3Device complexity
If the shared BSG is used to control all BSTs in a block, then the device complexity is reduced, but the parasitic capacitance and coupling effects increase
Solution Approach 1:
The patent assigns dedicated BSGs and TSGs to each block, physically separating the select gates through dielectric trenches. This segmentation reduces parasitic capacitance and coupling effects between adjacent blocks by isolating their respective select gates, thereby improving signal integrity and reducing interference while maintaining manageable device complexity through modular architecture.
Data Source
AI summary
In a method for manufacturing a memory device, a plurality of first insulating layers and a bottom select gate (BSG) layer are formed over a substrate, where the first insulating layers are disposed between the substrate and the BSG layer. One or more first dielectric trenches are formed to pass through the BSG layer and the first insulating layers, and extend in a length direction of the substrate. A plurality of word line layers and a plurality of second insulating layers are formed over the BSG layer, where the second insulating layers are disposed between the BSG layer and the word line layers. One or more common source regions are formed over the substrate to extend in the length direction of the substrate, and further extend through the BSG layer, the first insulating layers, the word line layers, and the second insulating layers.