3D NAND Subblock Operation for Mixed-Capacity Memory Blocks
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Solution Overview
Problem
The increasing number of layers in 3D NAND memory devices poses a challenge in accommodating both high and low capacity memory cell array blocks without significant firmware updates.
Innovation Solution
A memory device with a memory cell array block divided into two subblocks, each with distinct programming and erasing strategies based on the state of the other subblock, using a control logic to manage operations efficiently.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the number of layers in stacked structure is increased to increase capacity, then storage capacity is improved, but the ability to accommodate small capacity memory cell array blocks deteriorates
Solution Approach 1:
The memory cell array block is divided into multiple subblocks (first subblock and second subblock), each capable of independent operation. This segmentation allows the system to select and operate only the required number of subblocks based on capacity needs, enabling both high-capacity (all subblocks active) and low-capacity (fewer subblocks active) configurations within the same physical structure.
2Ease of operation
If block mode is used to perform operations, then operational simplicity is improved, but operational efficiency and longevity deteriorate
Solution Approach 1:
The system dynamically switches between block mode and subblock mode based on operational requirements. In block mode, all subblocks operate together for simple bulk operations. In subblock mode, only necessary subblocks are activated for more efficient targeted operations, optimizing both simplicity and efficiency depending on the task.
3Productivity
If subblock mode is used to perform operations, then operational efficiency is improved, but control complexity deteriorates
Solution Approach 1:
The control logic pre-establishes the correspondence relationships between subblocks and manages their states in advance. Before operations begin, the system determines which subblocks need to be active and configures their interrelationships, simplifying the control process during actual operations while maintaining high efficiency.
Data Source
AI summary
A memory device includes at least one memory cell array block and a control logic. The memory cell array block includes multiple layers of memory cells and word line layers provided corresponding to individual layers of memory cells. The memory cell array block is divided into at least two memory cell array subblocks, each subblock comprising a number of layers of memory cells and word line layers provided corresponding to individual layers of memory cells. The control logic is coupled to the memory cell array block, and configured to: erase, read or program the memory cell array block using a block mode or a subblock mode, and when the memory cell array block is erased, read, or programmed under the subblock mode, determine, at least based on a state of one of the two memory cell array subblocks, an operation strategy of the other memory cell array subblock.