3D NAND Substrate Doping for Stable Resistivity and Low Leakage
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Solution Overview
Problem
Existing memory devices face challenges in maintaining consistent electrical characteristics, leading to variations in resistivity and device performance, particularly in 3D NAND memory cell arrays, which affect breakdown voltage and leakage currents.
Innovation Solution
The use of substrates doped with both p-type and n-type impurities, where the concentration of n-type impurities is lower than p-type impurities, with specific ranges of 2×10^14 to 1.5×10^15 atoms/cm^3 for n-type and 9×10^14 to 2×10^15 atoms/cm^3 for p-type, to achieve a stable resistivity of 14 to 17 Ω·cm, thereby reducing variations in device characteristics.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a substrate is used with conventional doping (only p-type or only n-type impurities), then the manufacturing process is simple, but the electrical characteristics show large variations including resistivity, breakdown voltage, and leakage current
Solution Approach 1:
The substrate employs a composite doping structure combining both p-type impurities (first concentration: 1×10^15 to 5×10^15 atoms/cm³) and n-type impurities (second concentration: 1×10^14 to 5×10^14 atoms/cm³) within the same semiconductor material. This composite approach creates a balanced electrical environment that reduces variations in resistivity, breakdown voltage, and leakage current, thereby improving reliability without requiring multiple separate substrates or complex multi-layer structures
Solution Approach 2:
The invention optimizes specific doping parameters by controlling the concentration ratios of p-type and n-type impurities. The p-type impurity concentration is maintained at 1×10^15 to 5×10^15 atoms/cm³ while n-type impurity concentration is kept at 1×10^14 to 5×10^14 atoms/cm³, creating a parameter combination that achieves stable electrical characteristics including controlled resistivity (10-20 Ω·cm) and reduced leakage current, thus resolving the contradiction between reliability and complexity
2Reliability
If the n-type impurity concentration is increased to reduce resistivity variation, then resistivity stability improves, but leakage current increases
Solution Approach 1:
The invention precisely controls the n-type impurity concentration within the range of 1×10^14 to 5×10^14 atoms/cm³, which is sufficiently high to provide resistivity stability (maintaining resistivity between 10-20 Ω·cm) but low enough to prevent excessive leakage current. This parameter optimization resolves the trade-off by finding the optimal concentration point that balances both requirements
Solution Approach 2:
The substrate creates different local electrical environments by distributing p-type and n-type impurities with different concentrations throughout the semiconductor structure. The p-type impurities (higher concentration: 1×10^15 to 5×10^15 atoms/cm³) provide the primary electrical characteristics and resistivity control, while the n-type impurities (lower concentration: 1×10^14 to 5×10^14 atoms/cm³) provide local stability without causing harmful leakage effects, thus resolving the contradiction through spatial and functional differentiation
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach results in reduced resistivity variation, minimizing breakdown voltage and leakage current fluctuations, and enhancing overall device performance by maintaining consistent electrical characteristics.
Implementation Method 1
The substrate includes p-type impurities and n-type impurities, a concentration of the n-type impurities in the substrate is lower than a concentration of the p-type impurities in the substrate
Implementation Method 2
achieve a stable resistivity of 14 to 17 Ω·cm, thereby reducing variations in device characteristics
Data Source
AI summary
A memory device includes a substrate, a three-dimensional (3D) NAND memory cell array on the substrate, and a peripheral circuit including a transistor on the substrate. The substrate includes p-type impurities and n-type impurities, a concentration of the n-type impurities in the substrate is lower than a concentration of the p-type impurities in the substrate, and the concentration of the n-type impurities in the substrate is about 2×1014 atoms/cm3 to about 1.5×1015 atoms/cm3 while the concentration of the p-type impurities in the substrate is about 9×1014 atoms/cm3 to about 2×1015 atoms/cm3.