3D NAND Super Block Parity Layout for Data Integrity
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Solution Overview
Problem
Conventional 3D NAND-type flash memory technologies face challenges in data integrity and accuracy due to complex manufacturing structures and shared control circuits, leading to data errors during programming and reading, which require effective error correction mechanisms without increasing flash memory or buffer space.
Innovation Solution
Implementing a RAID-like error correction mechanism that encodes data to generate parity check codes and stores them in separate super blocks of 3D NAND-type flash memory modules, using a flash memory controller with a microprocessor and codec to manage data access and error correction without occupying additional memory space.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If conventional 3D NAND-type flash memory structure is used, then storage density and capacity are increased, but data errors occur due to shared control circuits and complex manufacturing
Solution Approach 1:
The patent segments the flash memory into multiple independent planes, where each plane has its own dedicated control circuit. This segmentation isolates errors to specific planes rather than affecting the entire memory system, thereby maintaining data integrity while preserving high storage capacity through the multi-plane architecture.
Solution Approach 2:
The patent implements different error correction strategies for different data types: SLC blocks use one error correction approach while MLC blocks use another. This local quality differentiation allows optimized error handling for each cell type's characteristics, improving overall data reliability without compromising storage density.
2Reliability
If error correction mechanism is added to correct data errors, then data integrity is improved, but flash memory space and buffer memory space are occupied
Solution Approach 1:
The patent merges the error correction code storage with the existing flash memory structure by utilizing spare areas within the same physical blocks. Instead of adding separate dedicated ECC storage regions, the correction codes are integrated into the existing memory layout, avoiding additional space occupation while maintaining comprehensive error correction capability.
Solution Approach 2:
The patent stores error correction information in the time dimension rather than consuming additional space dimension. By implementing incremental error correction where codes are generated and applied progressively during programming operations, the system avoids needing proportional additional storage space while achieving robust error correction.
3Reliability
If RAID-like error correction mechanism is implemented, then data errors are corrected effectively, but circuit complexity increases
Solution Approach 1:
The patent implements self-service error correction where the flash memory controller autonomously generates and applies correction codes without requiring complex external intervention. The controller monitors programming operations in real-time and automatically corrects errors as they occur, reducing the need for complex external error correction circuits while maintaining high data integrity.
Solution Approach 2:
The patent performs preliminary error correction by generating correction codes during the programming phase itself, before data retrieval is needed. This preliminary action allows errors to be corrected proactively rather than requiring complex detection and correction circuits to operate during read operations, thereby reducing overall circuit complexity.
Data Source
AI summary
A method for accessing a flash memory module is provided. The flash memory module is a 3D flash memory module including a plurality of flash memory chips, each flash memory chip includes a plurality of blocks, each block includes a plurality of pages, and the method includes: configuring the flash memory chips to set at least a first super block and at least a second super block of the flash memory chips; and allocating the second super block to store a plurality of temporary parities generated when data is written into the first super block.