3D NAND Gate Electrode Layout With Support Vias for Faster Access
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Solution Overview
Problem
Existing semiconductor devices face challenges in increasing data storage capacity while maintaining efficient data access and processing speeds.
Innovation Solution
A semiconductor device design featuring a gate electrode structure with insulation and support structures that enhance data storage capacity, including a channel structure with division patterns and through vias, and a memory cell structure with peripheral circuit wirings and a controller for control operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory cells are 3-dimensionally stacked to increase data storage capacity, then storage capacity is improved, but device complexity increases
Solution Approach 1:
The gate electrode structure is divided into multiple gate electrodes (first gate electrode, second gate electrode, third gate electrode) stacked in the first direction, with each gate electrode serving distinct functional purposes. This segmentation allows independent control and optimization of different memory cell regions, managing complexity through modular design while achieving high storage capacity.
Solution Approach 2:
The patent transitions from planar 2D memory cell layout to 3D vertical stacking architecture. Memory cells are arranged in multiple layers along the first direction (vertical dimension), with gate electrodes stacked above each other. This dimensional transition dramatically increases storage capacity within the same footprint while the structured layering manages the inherent complexity through systematic organization.
2Quantity of substance
If gate electrodes are spaced apart in the first direction to form 3D structure, then storage capacity is improved, but manufacturing precision requirements increase
Solution Approach 1:
The gate electrodes are formed with predetermined spacing in the first direction during the manufacturing process. The first gate electrode, second gate electrode, and third gate electrode are sequentially formed at specific heights, with each subsequent gate electrode positioned relative to the previous ones. This preliminary positioning establishes the 3D structure early in fabrication, enabling precise control of inter-gate distances and reducing later alignment complexity.
Solution Approach 2:
The insulation pattern structure serves as an intermediary element between the gate electrodes and other components. It extends through a portion of the gate electrode structure and provides a reference framework that facilitates precise positioning of through vias and support structures. This intermediary structure mediates the spatial relationships, ensuring manufacturing precision in the 3D stacked configuration.
3Productivity
If division patterns are added at opposite sides of gate electrode structure, then data access efficiency is improved, but device complexity increases
Solution Approach 1:
Division patterns are formed at opposite sides of the gate electrode structure in the third direction, extending in the second direction. These division patterns segment the memory array into distinct regions, enabling independent access to different data blocks. This segmentation improves data access efficiency by allowing parallel operations on separated regions while maintaining a regular, manageable structural repetition that controls complexity.
4Reliability
If through vias are formed through insulation pattern structure, then electrical connection is improved, but manufacturing precision requirements increase
Solution Approach 1:
The insulation pattern structure acts as an intermediary that extends through a portion of the gate electrode structure, providing a pre-formed template for through via placement. The through vias are formed by aligning with this intermediary structure, which establishes precise spatial references. This approach ensures reliable electrical connections while reducing manufacturing precision requirements compared to forming vias without such guidance structures.
Data Source
AI summary
A semiconductor device includes a gate electrode structure, a channel, a division pattern, an insulation pattern structure, a through via, and a support structure. The gate electrode structure is on a substrate, and includes gate electrodes stacked in a first direction perpendicular to the substrate. Each of the gate electrodes extends in a second direction parallel to the substrate. The channel extends through the gate electrode structure. The division pattern is at each of opposite sides of the gate electrode structure in a third direction parallel to the substrate. The insulation pattern structure extends through the gate electrode structure. The through via extends through the insulation pattern structure. The support structure extends through the gate electrode structure between the insulation pattern structure and the division pattern. The support structure includes first and second extension portion extending in the second and third directions, respectively.