3D NAND Hybrid Bonding Contacts for Easier TAC Etching
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Solution Overview
Problem
Planar memory cell technologies face challenges in scaling due to limitations in feature size and increasing costs, necessitating the development of three-dimensional (3D) memory architectures to enhance memory density.
Innovation Solution
The implementation of through array contact (TAC) structures in 3D NAND memory devices, featuring an alternating layer stack with dielectric and conductor pairs, barrier structures, and through array contacts to facilitate vertical interconnects between memory arrays and peripheral circuits, reducing process complexity and manufacturing costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If planar memory cells are scaled to smaller sizes by improving process technology, then memory density is improved, but feature size approaches a lower limit making planar process and fabrication techniques challenging and costly
Solution Approach 1:
The patent transitions from planar (2D) memory cell architecture to three-dimensional (3D) memory architecture. The 3D memory device stacks memory cells vertically with alternating conductor/dielectric layers extending in the vertical direction, enabling higher density without further reducing lateral feature sizes. This dimensional change resolves the scaling limitation by utilizing the vertical dimension for additional memory capacity.
2Ease of operation
If through array contact structures are formed in alternating conductor/dielectric stacks, then vertical interconnects are achieved, but etching difficulty increases due to the alternating conductor/dielectric structure
Solution Approach 1:
The patent divides the through array contact formation process into two separate etching steps: first etching through the alternating dielectric stack (which is easier), then etching through the alternating conductor/dielectric stack (which is harder). This segmentation allows the simpler dielectric etch to be completed first, establishing a foundation for the subsequent conductor/dielectric etch, thereby managing the overall manufacturing complexity.
Solution Approach 2:
The patent performs preliminary actions by forming the alternating dielectric stack first, then forming the alternating conductor/dielectric stack on top of it. The dielectric layers are prepared and patterned before the conductor layers are added, creating a structured foundation that facilitates the subsequent formation of through array contacts through the combined structure.
3Quantity of substance
If alternating conductor/dielectric stacks are used in 3D memory devices, then memory density is enhanced, but manufacturing cost increases due to complex fabrication processes
Solution Approach 1:
The alternating conductor/dielectric stack structure serves multiple functions simultaneously: it provides memory cell formation, creates vertical interconnect pathways, and enables both array and peripheral circuit integration. This multi-functionality reduces the need for separate structures and processes, thereby managing manufacturing complexity and cost while achieving high density.
Data Source
AI summary
A three-dimensional (3D) NAND memory device includes a substrate, a staircase region including a first stack and a second stack, a barrier structure extending vertically through the first stack and laterally separating the first stack from the second stack, and a through array contact extending vertically through the first stack to the substrate. The first stack is disposed on the substrate and includes first and second dielectric layers arranged alternately in a vertical direction. The second stack is disposed on the substrate and includes conductor layers and third dielectric layers arranged alternately in the vertical direction. The barrier structure has an unclosed shape.