3D NAND Through-Array Contact Structure for Vertical Memory Interconnects
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Solution Overview
Problem
Planar memory cell technologies face challenges in scaling due to limitations in feature size and fabrication costs, leading to density constraints in memory devices.
Innovation Solution
The development of three-dimensional (3D) NAND memory devices with through array contact (TAC) structures, featuring a substrate with alternating dielectric and conductor layers, barrier structures, and slit structures to enable vertical interconnects and separate memory regions, allowing for efficient electrical connections and reduced manufacturing complexity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If planar memory cell scaling is pursued, then memory density is improved, but feature size approaches lower limit and fabrication becomes challenging and costly
Solution Approach 1:
The patent transitions from planar (2D) memory cell architecture to three-dimensional (3D) memory architecture. The memory array is stacked vertically with alternating dielectric and conductor layers forming multiple memory planes, enabling memory density scaling without further reducing lateral feature sizes. This vertical stacking approach resolves the contradiction by moving the scaling dimension from lateral to vertical.
2Quantity of substance
If planar memory cell scaling is pursued, then memory density is improved, but fabrication costs increase
Solution Approach 1:
By stacking memory arrays vertically in the third dimension, the patent achieves higher memory density without requiring proportionally more complex fabrication processes. The alternating layer stack can be formed using standard deposition and etching techniques, making the 3D structure manufacturable with existing process technology.
Solution Approach 2:
The memory array is segmented into multiple alternating dielectric and conductor layers, creating discrete memory planes that can be independently formed and controlled. This segmentation allows for modular fabrication where each layer pair can be processed separately, simplifying the overall manufacturing process compared to attempting to fabricate a monolithic 3D structure.
3Quantity of substance
If 3D memory architecture is implemented, then density limitation is addressed, but device complexity increases
Solution Approach 1:
The alternating dielectric and conductor layers serve multiple functions simultaneously: they form memory cells in different planes, provide electrical isolation between planes, establish vertical interconnect pathways, and create stacked capacitor structures. This multi-functionality reduces the need for separate dedicated structures for each function, thereby managing complexity.
Solution Approach 2:
The patent merges the formation of memory cells, isolation structures, and interconnect pathways into a single integrated alternating layer stack. Rather than separately fabricating these components, they are combined into one monolithic structure where dielectric layers provide both isolation and structural support, and conductor layers provide both word lines and vertical interconnects.
4Productivity
If vertical interconnects are implemented in 3D memory, then electrical connection efficiency is improved, but manufacturing complexity increases
Solution Approach 1:
Vertical interconnects are merged with the existing alternating layer stack structure. The conductor layers that form word lines in each memory plane also serve as vertical interconnect pathways when extended through multiple planes. This eliminates the need for separate via structures and reduces the number of fabrication steps required to create vertical electrical connections.
Solution Approach 2:
The conductor layers perform dual functions: they serve as word lines for controlling memory cells within each plane and simultaneously provide vertical interconnect pathways for signal transmission between planes. This multi-functionality achieves efficient electrical connections without requiring additional dedicated interconnect structures, thereby managing manufacturing complexity.
Data Source
AI summary
A memory device includes a first stack and a second stack, a barrier structure extending vertically through the first stack and laterally separating the first stack from the second stack, a through array contact structure extending vertically through the first stack, and a slit structure extending through the second stack along a first lateral direction perpendicular to a vertical direction and including a conductive structure. The first stack includes first dielectric layers and second dielectric layers arranged alternately in the vertical direction. The second stack includes conductor layers and third dielectric layers arranged alternately in the vertical direction. The barrier structure includes two parallel first sub-barrier structures.