3D NAND Through-Array Contact Structure for Vertical Interconnects
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Solution Overview
Problem
Planar memory cell technologies face challenges in scaling due to limitations in feature size and fabrication costs, necessitating a transition to three-dimensional (3D) memory architectures to enhance memory density.
Innovation Solution
The development of three-dimensional NAND memory devices with through array contact (TAC) structures, featuring a substrate with alternating dielectric and conductor layers, barrier structures, channel and slit structures, and through array contacts to facilitate vertical interconnects and reduce manufacturing complexity and costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If planar memory cell scaling continues, then manufacturing precision improves, but feature size approaches lower limit causing fabrication costs to increase
Solution Approach 1:
The patent transitions from planar (2D) memory cell architecture to three-dimensional (3D) memory architecture. The 3D memory device stacks memory cells vertically across multiple layers, enabling continued scaling and density improvement without further reducing lateral feature sizes, thereby avoiding the exponential cost increase associated with sub-lithographic scaling
2Quantity of substance
If planar memory cell feature size is reduced, then memory density improves, but fabrication complexity increases
Solution Approach 1:
By stacking memory cells in the vertical dimension rather than packing them laterally, the patent achieves high memory density with standardized fabrication processes. The alternating conductor/dielectric layers are formed using conventional deposition techniques, and the 3D structure emerges from layer-by-layer construction rather than complex planar patterning
Solution Approach 2:
The 3D memory structure is segmented into repeating units of alternating conductor and dielectric layers. Each layer pair forms a modular building block that can be fabricated using standardized processes, and multiple such blocks are stacked to achieve the desired memory density without increasing individual layer fabrication complexity
3Quantity of substance
If 3D memory architecture is implemented, then memory density improves, but device structure complexity increases
Solution Approach 1:
The alternating conductor/dielectric layer structure serves multiple functions simultaneously: the conductor layers form bit lines and word lines for memory cell addressing, the dielectric layers provide electrical isolation and serve as tunnel barriers for charge storage, and the stacked configuration enables three-dimensional memory density. This multi-functional design reduces the need for separate specialized structures
4Productivity
If through array contact structure is used, then interconnect efficiency improves, but manufacturing precision requirements increase
Solution Approach 1:
The through array contacts are formed by drilling or etching holes through the entire alternating layer stack before subsequent metallization and planarization steps. By establishing the contact positions early in the fabrication sequence, the patent ensures precise alignment with underlying substrate contacts and overlying interconnect layers, as the contact locations are fixed before any lateral shifting or deformation occurs
Data Source
AI summary
A three-dimensional (3D) memory device includes a staircase region including a first stack and a second stack, a barrier structure extending vertically through the first stack and laterally separating the first stack from the second stack, and a through array contact extending vertically through the first stack. The first stack includes first and second dielectric layers arranged alternately in a vertical direction. The second stack includes conductor layers and third dielectric layers arranged alternately in the vertical direction. The barrier structure includes an unclosed shape.