3D NAND Flash Top Dummy Layer Programming Control
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Solution Overview
Problem
Conventional 3D NAND flash architectures face issues with programming interference and coupling interference due to inferior subthreshold slope of top layers, leading to inconsistent threshold voltage control and reduced programming efficiency, especially at lower temperatures.
Innovation Solution
Defining the top layer of bit lines as a top dummy layer and applying a first voltage on the top dummy layer of select bit lines during programming to turn on the dummy layer while turning off upper select gates of unselect bit lines, thereby reducing leakage current and interference.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the top layer of bit lines is defined as a top dummy layer and a first voltage is applied to turn it on during programming, then the subthreshold slope of upper select gates is enhanced and programming interference is reduced, but the device complexity increases due to the additional dummy layer structure
Solution Approach 1:
The top dummy layer acts as an intermediary element between the upper select gates and the storage layers. By applying a first voltage to turn on the top dummy layer during programming, it mediates the electrical characteristics to enhance the subthreshold slope of upper select gates, thereby reducing programming interference without requiring fundamental changes to the core memory structure
Solution Approach 2:
The invention changes the voltage parameter applied to the top dummy layer during programming operations. By dynamically adjusting the voltage state of the top dummy layer (turning it on with a first voltage), the electrical characteristics of the upper select gates are modified, improving the subthreshold slope and reducing interference while maintaining structural simplicity
2Productivity
If a first voltage is applied on the top dummy layer of select bit lines to turn on the dummy layer during programming, then the threshold voltage window is increased and programming efficiency is improved, but the use of energy increases due to additional voltage application
Solution Approach 1:
The top dummy layer is turned on only partially or selectively during specific programming operations where it provides the most benefit. By applying the first voltage only when needed for enhancing upper select gate characteristics and reducing interference, the energy consumption is minimized while still achieving improved programming efficiency and threshold voltage window
3Productivity
If the upper select gates are fully turned on by applying voltage Vtsg, then the programming efficiency of the select string is increased, but programming interference and coupling interference are generated between layers
Solution Approach 1:
The top dummy layer is selectively activated only for select bit lines during programming operations, while unselect bit lines maintain their original voltage state. This localized application of the first voltage to specific regions (select strings) enhances programming efficiency for the target location without generating excessive interference in non-target areas, thereby resolving the contradiction between efficiency and interference
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the subthreshold slope of upper select gates, improves temperature characteristics, reduces programming interference, and increases the threshold voltage window, allowing for more efficient programming with fewer impulses and lower voltage.
Implementation Method 1
applying a first voltage on a first top dummy layer of a select bit line to turn on the first top dummy layer... enhances the subthreshold slope of upper select gates
Implementation Method 2
applying a first voltage on a first top dummy layer of a select bit line to turn on the first top dummy layer of the select bit line... reduces programming interference
Data Source
AI summary
An operation method for a 3D NAND flash having a plurality of bit lines, wherein the plurality of bit lines comprises a plurality of layers, the operation method includes defining a plurality of upper layers of the plurality of bit lines of the 3D NAND flash as a plurality of upper select gates and a top layer of the plurality of bit lines of the 3D NAND flash as a top dummy layer; and applying a first voltage on a first top dummy layer of a select bit line of the plurality of bit lines to turn on the first top dummy layer of the select bit line of the plurality of bit lines when programming.