3D NAND Top Select Gate Structure for Threshold Voltage Stability
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Solution Overview
Problem
Scaling of planar memory cells faces challenges due to process technology limitations and reliability issues, limiting the density and performance of memory devices.
Innovation Solution
A method for forming a three-dimensional (3D) memory device by creating an alternating dielectric stack, forming channel holes, and disposing a top select gate (TSG) with specific dielectric and conductive layers to improve the top select transistor's performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If planar memory cells are scaled down to reduce die size, then storage density increases, but manufacturing cost increases and reliability deteriorates due to process technology limitations
Solution Approach 1:
The patent transitions from planar (2D) memory architecture to three-dimensional (3D) vertically stacked memory architecture. Multiple memory cells are stacked vertically along the thickness direction, enabling higher storage density without further lateral scaling. This dimensional change avoids the reliability issues associated with continued planar scaling while maintaining manufacturing feasibility.
Solution Approach 2:
The 3D memory structure divides the memory array into multiple vertically stacked memory strings, with each string containing multiple memory cells. This segmentation allows independent control and processing of memory cells, improving reliability by isolating defects and enabling selective operation of individual cells or groups of cells.
2Quantity of substance
If planar memory cells are scaled down to reduce die size, then storage density increases, but manufacturing cost increases due to process technology limitations
Solution Approach 1:
By stacking memory cells vertically in three dimensions, the patent achieves higher storage density without requiring continued scaling of lateral dimensions. This approach uses standard fabrication processes to create vertical structures, avoiding the increased manufacturing complexity and cost associated with advanced planar scaling techniques.
3Device complexity
If top select transistor structure is simplified, then device complexity decreases, but threshold voltage stability deteriorates affecting switching performance
Solution Approach 1:
The top select transistor employs a composite gate structure combining multiple dielectric layers (first gate dielectric layer, second gate dielectric layer) with conductive layers. This composite structure enables independent optimization of each layer's properties to achieve both structural simplicity and threshold voltage stability, with the first dielectric layer providing stable threshold voltage and the second providing switching control.
Solution Approach 2:
The patent applies different dielectric materials with specific properties to different regions of the gate structure. The first gate dielectric layer uses material optimized for threshold voltage stability, while the second gate dielectric layer uses material optimized for switching performance. This local differentiation of material properties allows the simplified transistor structure to achieve both reliability and functionality.
Data Source
AI summary
The present disclosure provides a method for forming a three-dimensional (3D) memory device. The method includes disposing an alternating dielectric stack that includes first dielectric layers and second dielectric layers alternatingly stacked on the substrate; forming a channel structure penetrating through the alternating dielectric stack in a first direction perpendicular to the substrate. The channel structure includes a charge trapping layer extending in the first direction. The method also includes removing at least one second dielectric layer at a top portion of the alternating dielectric stack to form a top select gate (TSG) cut tunnel and to expose a portion of the charge trapping layer in a second direction parallel to the substrate. The method further includes removing the exposed portion of the charge trapping layer inside the TSG cut tunnel; and disposing a TSG conductive layer inside the TSG cut tunnel.