3D NAND Top Select Gate Staircase Layout for Gate Connectivity
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Solution Overview
Problem
In 3D semiconductor devices, such as 3D NAND memory devices, the formation of top select gates (TSG) can lead to non-functional gate layers due to process limitations, reducing storage capacity as TSG cut structures divide them into isolated sections.
Innovation Solution
A semiconductor device design featuring alternating stacks of conductive and dielectric layers with staircase structures, where TSG cut structures have a shorter length than gate layers, allowing them to maintain functionality and form TSG electrodes, and contact structures ensure continuous operation of gate layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If TSG cut structures are used to separate TSG layers into multiple TSG electrodes, then the select gate functionality is improved, but the gate layers are divided into isolated sections which reduces storage capacity
Solution Approach 1:
The TSG layers are segmented into multiple TSG electrodes by the TSG cut structure, which extends through the TSG layers to divide them into separate functional sections. This segmentation allows independent control of different electrode groups while maintaining overall device functionality.
Solution Approach 2:
The gate layers that are isolated by the TSG cut structure are reconnected through a second dimension - specifically, through conductive connections in the horizontal plane (parallel to substrate) that bypass the vertical isolation created by the TSG cut. This dimensional transition restores connectivity without compromising the vertical select gate function.
2Manufacturing precision
If TSG cut structures extend through the entire stack, then complete separation of TSG electrodes is achieved, but gate layer connectivity is lost reducing device performance
Solution Approach 1:
The TSG cut structure segments the TSG layers into distinct electrode groups with precise separation, achieving clean isolation between different select gate electrode sections while maintaining control over the segmentation process.
Solution Approach 2:
Gate layer connectivity is restored by creating conductive paths in the horizontal dimension that connect gate sections separated by the vertical TSG cut structure, allowing current to flow around the isolation region rather than through it.
3Reliability
If the number of TSG layers is increased to enhance select gate control, then device complexity increases, but process limitations cause more non-functional gate layers
Solution Approach 1:
Increasing the number of TSG layers is achieved through systematic segmentation of the gate stack into multiple functional layers, each contributing to select gate control. The TSG cut structure enables this multiplication by providing a framework for creating multiple independently controllable electrode sections.
Data Source
AI summary
Systems, devices, and methods for managing top select gates in a semiconductor device are provided. In one aspect, a semiconductor device includes a first stack of conductive layers and isolating layers alternating with each other, and a second stack of dielectric layers and isolating layers alternating with each other. The second stack is connected to the first stack. A first portion of the first stack includes: one or more top select gate (TSG) layers of the conductive layers in a first part, and one or more conductive layers of the conductive layers in a second part. The first part includes a first staircase structure having one or more first stairs corresponding to the one or more TSG layers. The second part includes a second staircase structure having one or more second stairs. The first staircase structure and the second staircase structure are separated by a separation structure.