3D NAND Trim Control via Selective Multiplexing
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Solution Overview
Problem
Current 3D NAND memory devices face challenges in flexibly controlling trim parameters for word lines due to process variations and design differences, leading to performance degradation for memory cells with varying electrical characteristics.
Innovation Solution
A control method and system that utilize multiplexers and decoders to selectively apply trim settings, such as voltage levels and timing controls, to individual word lines within a memory block, allowing for customized trim parameter adjustments for each word line to optimize programming operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a single trim setting is applied to all word lines, then device complexity is reduced, but programming performance deteriorates due to process variations and electrical characteristic differences among word lines
Solution Approach 1:
The patent divides the trim control into multiple independent trim settings (first trim setting, second trim setting, third trim setting) corresponding to different word lines or word line groups. Each trim setting can be independently selected and applied, allowing customized voltage level adjustments for each segment rather than a uniform global trim, thus resolving the contradiction between simplified control and performance optimization.
Solution Approach 2:
The patent applies different trim settings to different word lines or word line groups based on their specific electrical characteristics and process variations. Each word line receives a locally optimized trim setting tailored to its performance needs, enabling localized performance enhancement without requiring complex global control mechanisms.
2Reliability
If multiple trim settings are applied to different word lines, then programming performance is improved, but device complexity increases due to additional control circuitry
Solution Approach 1:
The patent implements a unified trim control mechanism that can selectively apply different trim settings through a single control interface. The same control circuitry serves multiple functions by selecting from different trim settings based on word line requirements, avoiding the need for separate dedicated control circuits for each trim setting and thus limiting the increase in device complexity.
3Ease of operation
If trim parameters are globally adjusted, then control simplicity is maintained, but performance degradation occurs for word lines with varying electrical characteristics
Solution Approach 1:
The patent transitions from a static global trim approach to a dynamic selective trim approach. The system can dynamically select which trim setting to apply to which word line based on real-time performance requirements and electrical characteristics, providing operational flexibility while maintaining control simplicity through a unified selection mechanism.
Data Source
AI summary
The present disclosure provides a three-dimensional NAND memory device, comprising memory cells coupled to a plurality of word lines and configured to store data, a row decoder configured to decode an address of a word line from the plurality of word lines, and a controller coupled to the array of memory cells. The controller includes a first multiplexer configured to receive a first plurality of trim selections, while each of the first plurality of trim selections is associated with a first trim parameter and each of the first plurality of trim selections corresponds to each of the plurality of word lines, respectively. The controller also includes a second multiplexer configured to receive a first plurality of trim settings, while each of the first plurality of trim settings corresponds to a value associated with the first trim parameter.