3D NAND Memory Stack With Under-Array Logic and Vertical Interconnects
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Solution Overview
Problem
Conventional microelectronic device designs face challenges in reducing size and improving performance due to processing conditions and configurations of control logic devices within memory devices, particularly in 3D NAND Flash memory devices, which limit the horizontal footprint and hinder advancements in memory cell speed, data transfer rates, and power consumption.
Innovation Solution
The design incorporates a microelectronic device structure with a control logic region, a memory array region, and interconnect regions, where the memory array region features vertically alternating conductive and insulating structures, and source structures overlying the stack structure, coupled with digit line structures, allowing for improved control logic device configurations and reduced thermal budget constraints during fabrication.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If conventional processing conditions are used for forming memory array over base control logic structure, then control logic devices can be formed, but the configurations and performance of control logic devices are limited
Solution Approach 1:
The device is divided into a base control logic structure and a memory array structure that are formed separately and then combined. The memory array is formed on a separate substrate first, then bonded to the control logic structure, allowing each component to be optimized independently without processing condition conflicts.
Solution Approach 2:
The invention transitions from a planar integration approach to a three-dimensional stacked architecture. The memory array is vertically stacked over the control logic structure, enabling independent formation and optimization of each layer with different processing conditions, thereby increasing configuration flexibility while reducing processing constraints.
2Adaptability or versatility
If quantities, dimensions, and arrangements of control logic devices are increased to improve functionality, then more functions can be provided, but the horizontal footprint of the memory device increases
Solution Approach 1:
The control logic devices are arranged in a three-dimensional stacked configuration rather than a planar layout. Multiple tiers of control logic devices are vertically stacked, allowing increased functionality and more control logic devices to be integrated without increasing the horizontal footprint of the device.
Solution Approach 2:
Control logic devices are nested vertically within the stacked structure, with multiple tiers arranged one above another. This nested arrangement allows multiple functional units to occupy the same horizontal space by utilizing the vertical dimension, thereby reducing the overall horizontal footprint while maintaining enhanced functionality.
3Quantity of substance
If conventional vertical memory array architectures are used, then memory density can be increased, but processing conditions limit performance improvements
Solution Approach 1:
The memory array is segmented into multiple independent memory strings that are vertically stacked. Each memory string can be independently formed and optimized, allowing high memory density through vertical stacking while maintaining reliable performance by ensuring each segment meets performance requirements through independent processing optimization.
Data Source
AI summary
A microelectronic device comprises a memory array region, a control logic region underlying the memory array region, and an interconnect region vertically interposed between the memory array region and the control logic region. The memory array region comprises a stack structure comprising vertically alternating conductive structures and insulating structures; vertically extending strings of memory cells within the stack structure; at least one source structure vertically overlying the stack structure and coupled to the vertically extending strings of memory cells; and digit line structures vertically underlying the stack structure and coupled to the vertically extending strings of memory cells. The control logic region comprises control logic devices for the vertically extending strings of memory cells. The interconnect region comprises structures coupling the digit line structures to the control logic devices. Methods of forming a microelectronic device, and memory devices and electronic systems are also described.