3D NAND Memory Device Vertical Channel Fabrication
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Solution Overview
Problem
Planar memory cell fabrication techniques face challenges and cost issues as feature sizes approach limits, necessitating a more efficient method to increase memory density.
Innovation Solution
A 3D NAND memory device is formed by etching a substrate to create an array of protruding islands, followed by a gate dielectric layer, an underlying sacrificial layer, and an alternating dielectric stack, with channel holes penetrating the stack to accommodate a memory layer connected to each island, reducing thermal requirements and improving channel region quality.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If planar memory cell fabrication techniques are used to scale to smaller sizes, then memory density can be improved, but process complexity and cost increase significantly as feature sizes approach lower limits
Solution Approach 1:
The patent transitions from planar (2D) memory cell fabrication to three-dimensional (3D) fabrication by forming vertical channel holes through alternating dielectric stacks and creating channel regions that extend vertically, thereby increasing memory density without further reducing lateral feature sizes and avoiding the associated process complexity and cost increases
2Reliability
If epitaxial growth is used to form channel regions, then channel quality can be improved, but thermal requirements and process complexity increase
Solution Approach 1:
The patent replaces the thermal epitaxial growth process with a mechanical/sputtering-based deposition process to form the channel regions, thereby maintaining channel quality while significantly reducing thermal requirements and simplifying the fabrication process
3Quantity of substance
If feature sizes are reduced to increase memory density, then memory capacity improves, but fabrication precision and control become increasingly difficult
Solution Approach 1:
The patent forms vertical channel holes through alternating dielectric stacks with controlled thicknesses, achieving high memory capacity through vertical stacking rather than lateral scaling, thereby maintaining fabrication precision while increasing memory capacity
Solution Approach 2:
The patent controls the thickness parameters of alternating dielectric layers (first dielectric layer, second dielectric layer, third dielectric layer) to precisely define channel hole dimensions and positions, achieving high memory capacity without compromising fabrication precision
Data Source
AI summary
Embodiments of through array contact structures of a 3D memory device and fabricating method thereof are disclosed. The method comprises: forming a recess region in a substrate including multiple protruding islands; forming a gate dielectric layer to cover top surfaces and sidewalls of the multiple protruding islands and a top surface of the recess region of the substrate; forming an underlying sacrificial layer on the gate dielectric layer to surround the sidewalls of the multiple protruding islands; forming an alternating dielectric stack including multiple alternatively stacked insulating layers and sacrificial layers on the underlying sacrificial layer and the multiple protruding islands; forming multiple channel holes penetrating the alternating dielectric stack, each channel hole is located corresponding to one of the multiple protruding islands; and forming a memory layer in each channel hole, wherein a channel layer of the memory layer is electrically connected with a corresponding protruding island.