3D NAND Vertical Plug Structure for Reliable Cell Integration
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Solution Overview
Problem
The existing 3D nonvolatile memory devices face challenges in improving operational reliability due to physical scaling limits and the need for enhanced structural designs to increase memory cell integration.
Innovation Solution
A semiconductor device with a gate stacked structure and vertical plug patterns, including insulating and conductive layers, separation patterns, and charge trap layers, is developed to enhance memory cell integration and reliability, involving a method of manufacturing that includes forming holes, separation patterns, blocking insulating layers, charge trap layers, and channel layers to create a vertical structure for improved memory cell formation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If 2D nonvolatile memory device structure is used, then manufacturing process is simpler, but memory cell integration is limited due to physical scaling limits
Solution Approach 1:
The patent transitions from a 2D memory structure to a 3D vertical structure by forming holes extending in the vertical direction through the gate stacked structure, with plug patterns and charge trap layers arranged vertically. This dimensional change enables increased memory cell integration density while maintaining manufacturing feasibility through sequential layer formation processes.
2Quantity of substance
If 3D nonvolatile memory device structure is used, then memory cell integration is improved, but operational reliability deteriorates due to structural complexity
Solution Approach 1:
The patent divides the vertical plug structure into distinct functional segments: blocking insulating layer, first charge trap layer, tunnel insulating layer, and second charge trap layer. Each segment performs a specific function (charge blocking, charge trapping, charge injection, and additional charge trapping), which improves operational reliability by ensuring proper charge management while maintaining high integration density.
3Quantity of substance
If separation patterns are added to create vertical plug structures, then memory cell integration is improved, but device complexity increases
Solution Approach 1:
The patent combines multiple functions into the separation patterns, which serve both as structural dividers to create vertical plug regions and as foundational layers for subsequent charge trap and insulating layer formation. This merging reduces the need for additional separate structures, managing device complexity while achieving improved memory cell integration.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The proposed semiconductor device and manufacturing method increase memory cell integration and operational reliability by creating a vertical structure with optimized plug patterns and layers, addressing the scaling limitations of existing 3D nonvolatile memory devices.
Implementation Method 1
forming a first separation pattern and a second separation pattern from the first preliminary separation pattern and the second preliminary separation pattern, respectively, by performing an oxidization process, wherein the first separation pattern and the second separation pattern protrude toward a center of the hole
Data Source
AI summary
Provided herein may be a semiconductor device and a method of manufacturing the same. The semiconductor device may include a gate stacked structure including insulating layers and conductive layers that are alternatingly stacked, a hole extending in a vertical direction into the gate stacked structure, and including a first sidewall and a second sidewall facing each other, a first separation pattern and a second separation pattern that contact a boundary portion between the first sidewall and the second sidewall, the first and second separation patterns facing each other and extending in the vertical direction, a first plug pattern contacting the first sidewall and extending in the vertical direction, and a second plug pattern contacting the second sidewall and extending in the vertical direction.