3D NAND Peripheral Circuit Layout With Reduced Through-Hole Vias
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Solution Overview
Problem
Existing nonvolatile memory devices face challenges in increasing data storage capacity and reducing chip size while improving operation performance.
Innovation Solution
A nonvolatile memory device with a highly integrated peripheral circuit configuration, featuring a horizontal semiconductor layer, stacked structures with interlayer insulating films and conductive films, and a reduced number of through-hole vias to enhance operation performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If traditional peripheral circuit configuration is used, then circuit functionality is maintained, but chip size increases and integration efficiency decreases
Solution Approach 1:
The patent transitions from a planar two-dimensional peripheral circuit layout to a three-dimensional configuration by placing control logic transistors in openings that extend through or through the stacked memory structures. This vertical integration allows peripheral circuits to occupy space in the third dimension, reducing the horizontal chip area required while maintaining circuit functionality.
Solution Approach 2:
The control logic transistors are nested within the stacked structure openings, effectively placing peripheral circuit elements inside the memory stack volume. This nesting approach allows the peripheral circuit to share the same vertical space as the memory cells, improving integration density and reducing overall chip size.
2Reliability
If more through-hole vias are used for peripheral circuit connections, then circuit connectivity is improved, but manufacturing complexity and cost increase
Solution Approach 1:
The stacked structure serves multiple functions: it provides memory cell storage and simultaneously acts as a support structure containing openings for peripheral circuit placement. The same vertical stack that stores data also houses the control logic, eliminating the need for separate peripheral circuit regions and reducing the total number of through-hole vias required for interconnections.
3Productivity
If peripheral circuits are placed on the same substrate plane, then manufacturing is simplified, but chip area increases and integration density decreases
Solution Approach 1:
The invention moves peripheral circuit elements from the two-dimensional substrate plane into the third dimension by placing control logic transistors in vertical openings through the stacked structures. This dimensional transition enables higher integration density without increasing the horizontal chip footprint, as the peripheral circuits now occupy vertical space rather than horizontal space.
Data Source
AI summary
A nonvolatile memory device includes a peripheral logic structure including a peripheral circuit on a substrate, a horizontal semiconductor layer extending along an upper surface of the peripheral logic structure, stacked structures arranged in a first direction on the horizontal semiconductor layer and including interlayer insulating films and conductive films alternately stacked in a direction perpendicular to the substrate, a first opening disposed between the stacked structures and included in the horizontal semiconductor layer to expose a part of the peripheral logic structure and a second opening arranged in a second direction, which differs from the first direction, from the first opening, included in the horizontal semiconductor layer, and disposed adjacent to the first opening. The peripheral logic structure includes a control transistor overlapping the second opening in a plan view and controlling operation of the plurality of stacked structures.