3D NAND Flash Memory Voltage Control During Erase
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Solution Overview
Problem
Existing semiconductor memory devices face challenges in efficiently managing voltages during the erase operation in 3D-stacked NAND flash memory, leading to increased power consumption and slower erase times due to the need for multiple charge pump circuits and optimal voltage control.
Innovation Solution
A semiconductor memory device with a detection circuit that generates flag signals based on applied voltages, allowing select gate lines, backgate lines, and dummy word lines to be set in an electrically floating state, reducing the need for multiple charge pump circuits and optimizing voltage application through coupling, thereby reducing power consumption and speeding up the erase operation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If multiple charge pump circuits are used to generate optimal voltages for all lines during erase operation, then voltage control precision is improved, but device complexity and power consumption increase
Solution Approach 1:
The patent extracts the voltage generation function from multiple charge pump circuits and concentrates it into a single charge pump circuit. The detection circuit identifies which lines require voltage boosting, and only those specific lines receive voltage through the single charge pump circuit, eliminating the need for multiple redundant voltage generation circuits.
Solution Approach 2:
The detection circuit automatically detects the voltage status of bit lines and source lines during erase operation, and the system self-adjusts by applying voltage only where needed. This self-service mechanism eliminates the need for external complex voltage control circuits, as the system autonomously manages its own voltage requirements.
2Reliability
If multiple charge pump circuits are used to ensure optimal voltage for each line, then erase operation reliability is improved, but power consumption increases
Solution Approach 1:
The patent extracts unnecessary voltage generation from the system by using a single charge pump circuit instead of multiple circuits. The detection circuit identifies exactly which lines need voltage boosting, eliminating redundant power consumption from unused charge pump circuits while maintaining reliable erase operation.
Solution Approach 2:
The patent dynamically changes the voltage parameter based on detection results. The detection circuit monitors voltage levels in real-time during erase operation, and the single charge pump circuit adjusts its output only when and where voltage boosting is detected as necessary, optimizing power consumption while ensuring operational reliability.
3Reliability
If voltages are applied to all lines during erase operation, then erase completeness is improved, but power consumption and time increase
Solution Approach 1:
The detection circuit provides self-service by automatically detecting which bit lines and source lines have insufficient voltage during erase operation. This enables the system to apply voltage selectively only to lines that need it, ensuring complete erase operation while minimizing power consumption by avoiding unnecessary voltage application to already adequately powered lines.
4Use of energy by moving object
If a single charge pump circuit is used with detection-based voltage application, then power consumption is reduced, but voltage control complexity increases
Solution Approach 1:
The patent merges the detection function and voltage control function into an integrated system. The detection circuit and single charge pump circuit work as a unified control mechanism, where detection results directly drive voltage application decisions. This merging reduces overall device complexity compared to having separate multiple charge pump circuits, while the detection-based approach simplifies the control logic by using automatic feedback.
Data Source
AI summary
According to one embodiment, a semiconductor memory device includes first and second select transistors, memory cells, a driver circuit, first transfer transistors, and a detection circuit. The memory cells are stacked above a semiconductor substrate. The driver circuit outputs a first voltage. The first transfer transistors transfer the first voltage to associated word lines and select gate lines. In data erase, the detection circuit detects a second voltage applied to bit lines and/or a source line and generates a flag in accordance with the detection result. The driver circuit changes the value of the first voltage in response to the flag to cut off the first transfer transistors.