3D NAND Best Read Voltage Scanning for Lower Read-Retry Latency
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Solution Overview
Problem
The high read latency and performance degradation in 3D NAND flash memory systems due to numerous read-retry operations with adjusted read reference voltages, which are not effectively managed by existing read-retry mechanisms.
Innovation Solution
Implementing methods and techniques for searching best read reference voltages through scan processes over multiple scan points, optimizing scan ranges, and using bit count differences to determine optimal read levels, reducing reliance on known data and minimizing flipping bits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple read-retry operations with adjusted read reference voltage values are performed, then the reliability of 3D NAND flash memory is improved, but the read latency increases and performance degrades
Solution Approach 1:
The patent performs a preliminary scan process to determine the optimal read reference voltage before actual read operations. By pre-determining the best read reference voltage through scanning multiple voltage points and evaluating bit count differences, the system avoids performing multiple read-retry operations with adjusted voltages, thus reducing read latency while maintaining reliability
Solution Approach 2:
The patent implements a feedback mechanism where the scan process evaluates bit count differences at various read reference voltage points to determine the optimal voltage. This feedback information about the best read reference voltage is then used to guide subsequent read operations, eliminating the need for multiple retry attempts and reducing overall read time
2Reliability
If a large number of read-retry operations are performed, then the reliability of data reading is improved, but the performance of the memory system degrades
Solution Approach 1:
The scan process is performed as a preliminary action before actual read operations to identify the optimal read reference voltage. This preliminary determination of the best voltage point ensures that subsequent read operations can be performed correctly on the first attempt, improving productivity by eliminating multiple retry operations while maintaining data reading reliability
Solution Approach 2:
The system performs self-diagnosis through the scan process, automatically determining the optimal read reference voltage by evaluating bit count differences at various voltage points. This self-service capability eliminates the need for external intervention or multiple retry attempts, thereby improving memory system performance while maintaining reliable data reading
Data Source
Figure 1
Figure 2A~2B
Figure 3
AI summary
A memory system includes a memory controller configured to determine a first best read offset of a first best read reference voltage with respect to a first default read reference voltage, and determine an anchor read reference voltage having a same offset as the first best read offset with respect to a second default read reference voltage. The first and second default read reference voltages are set for reading a page from a set of MLCs in a semiconductor memory device. A first scan range can be determined based on the anchor read reference voltage. A second best read offset of a second best read reference voltage with respect to the second read reference voltage can be determined by searching in the first scan range. A reading process can be performed to read the page from the set of MLCs based on the first and second best read reference voltages.