3D NAND Read Voltage Tuning for TLC Retention Errors
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Solution Overview
Problem
Three-dimensional flash memory experiences increased bit error rates and reduced data retention due to shifts in threshold voltage distribution curves, especially in triple-level cells, leading to reliability issues and complexity in error correction.
Innovation Solution
A memory device and read method that adjust bit line voltages during a second read operation to shift the threshold voltage distribution curve, improving data reliability by increasing the success rate of read operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If triple-level cells (TLC) are adopted to increase data storage density, then storage capacity is improved, but bit error rate increases and data retention capability deteriorates
Solution Approach 1:
The patent changes the bit line voltage parameter from a uniform first voltage to a set of different voltages (third, fourth, and fifth voltages) applied to different bit lines. This parameter change adjusts the threshold voltage distribution curve to compensate for charge loss in TLCs, thereby reducing bit error rate while maintaining high storage density
Solution Approach 2:
The patent applies different voltages to different bit lines based on their specific characteristics and the charge loss patterns of adjacent memory cells. This local quality approach allows targeted compensation for errors in specific regions while maintaining overall system performance
2Reliability
If error correcting codes (ECC) are adopted to maintain data reliability, then data retention is improved, but layout area increases and manufacturing cost increases
Solution Approach 1:
The patent performs preliminary action by adjusting bit line voltages before the read operation to prevent errors from occurring in the first place. By shifting the threshold voltage distribution curve in advance, the patent reduces the raw bit error rate, thereby reducing the burden on ECC circuits and allowing for simpler error correction implementations
Solution Approach 2:
The patent converts the harmful effect of charge loss and threshold voltage shifts into a benefit by using controlled voltage adjustments to deliberately shift the threshold voltage distribution curve. This transforms the underlying physical problem into a controllable parameter that can be used to improve read accuracy
3Productivity
If the number of program/erase cycles increases to utilize memory capacity, then storage utilization is improved, but data retention capability deteriorates due to increased errors
Solution Approach 1:
The patent introduces dynamics by making the bit line voltage adjustable and adaptable based on the memory cell state and read conditions. The voltage can be dynamically changed from the first voltage to different voltages in the set, allowing the system to adapt to degradation from program/erase cycles and maintain reliable operation over time
Data Source
AI summary
A memory device and a read method therefor are disclosed. The memory device includes first to third memory cell strings. The memory device is a three-dimensional NAND flash memory with high capacity and high performance. Each of the memory cell strings includes first to third memory cells. The read method includes: performing a first read operation of the memory device to the second memory cell in the second memory cell string, the first read operation includes applying a first bit line voltage to a first bit line, a second bit line, and a third bit line; in response to the failure of the first read operation, performing a second read operation of the memory device, the second read operation includes: applying a set of second bit line voltages to the first bit line, the second bit line and the third bit line.