3D NAND Vpass Disturb Reduction via Segmented Word Line Voltages

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Solution Overview

Problem

Vpass disturb occurs during programming operations in memory devices, where unselected cells can be inadvertently 'soft-programmed' due to the Vpass voltage applied to unselected word lines, especially when the isolation performance of the tunneling layer is poor, leading to potential errors in memory cell programming.

Innovation Solution

The solution involves applying different pass voltages to various unselected word lines during programming operations to minimize the electric field effect on unselected cells, thereby reducing the likelihood of Vpass disturb. This includes applying specific pass voltages to multiple layers of unselected word lines adjacent to the selected word line, with each layer receiving a distinct voltage level to control the programming process effectively.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of operation

If a single Vpass voltage is applied to all unselected word lines to minimize program disturbance, then the programming operation can be simplified, but Vpass disturb occurs on unselected cells due to electric field effects

Engineering Contradiction:
Improveprogramming operation simplicityVSAvoidmemory cell programming accuracy
Core Design Contradiction:
Ease of operationVSReliability

Solution Approach 1:

The patent divides unselected word lines into multiple groups (first group, second group, third group) and applies different pass voltages to each group. This segmentation allows the system to maintain programming simplicity while preventing Vpass disturb by tailoring the electric field conditions for each group of unselected cells.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Different pass voltages are applied to different groups of unselected word lines based on their specific positions and susceptibility to disturb. The first group receives a first pass voltage, the second group receives a second pass voltage, and the third group receives a third pass voltage, creating locally optimized conditions for each region.

Inventive Principle:
Principle #3Local quality

2Reliability

If multiple different pass voltages are applied to different groups of unselected word lines to reduce Vpass disturb, then programming accuracy is improved, but the complexity of the programming operation increases

Engineering Contradiction:
Improvememory cell programming accuracyVSAvoidprogramming operation complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

By segmenting unselected word lines into distinct groups that can be controlled independently, the patent manages complexity through organized classification. Each group receives a specific pass voltage level, making the complex multi-voltage scheme systematically manageable rather than chaotic.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent applies pass voltages selectively to different groups of unselected word lines rather than uniformly to all. This partial action approach focuses the complexity only where needed (on unselected lines) while leaving selected lines and their associated cells with simpler control, thereby containing the overall system complexity.

Inventive Principle:
Principle #16Partial or excessive action

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach effectively reduces Vpass disturb by managing the electric field across unselected cells, enhancing the accuracy and reliability of programming operations in memory devices, particularly in 3D NAND memory devices with complex word line configurations.

Implementation Method 1

the potential difference between the gate and the channel of the non-programmed cells can form an electric field. The magnitude of the electric field may not be large enough to allow electrons to easily enter a charge-trapping layer.

Methodology Applied
Scientific EffectElectric field: Electric Field

Data Source

PatentUS12260096B2Method of reducing Vpass disturb in 3D nand systems
Publication Date: 2025.03.25 YANGTZE MEMORY TECH CO LTD
  • US12260096B2 patent drawing
  • US12260096B2 patent drawing
  • US12260096B2 patent drawing

AI summary

The present disclosure provides a three-dimensional NAND memory device, comprising a NAND string including a memory cell to be inhibited to program, a word line driver, and a controller configured to control the word line driver to perform a programming operation on the memory cell controlled by a selected word line of a plurality of word lines including a first unselected word line adjacent to the selected word line, a first plurality of unselected word lines adjacent to the first unselected word line, and a second plurality of unselected word lines adjacent to the first plurality of unselected word lines. The programming operation includes applying a programming voltage signal to the selected word line; applying a first pass voltage to the first plurality of unselected word lines; and applying a second pass voltage to the second plurality of unselected word lines, the first pass voltage is different from the second pass voltage.