3D NAND Word Line Coupling via Slits and Height-Varied Support
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Solution Overview
Problem
Conventional 3D non-volatile memory devices face challenges in increasing integration density due to the complexity of patterning word lines into stepped shapes and the need for additional space for pass transistors, limiting the number of stacked word lines and overall integration.
Innovation Solution
A semiconductor device with a substrate featuring transistors in contact regions, a support body with varying heights, and stacked conductive layers separated by slits, allowing for efficient coupling of global and local word lines through slits to transistor junctions, thereby simplifying manufacturing and enhancing integration density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If word lines are patterned into a stepped shape to enable selective coupling, then the desired word line can be selected, but the manufacturing complexity increases and the number of processes increases
Solution Approach 1:
The device is segmented into multiple contact regions (first, second, third contact regions) with transistors positioned at different heights. This segmentation allows each contact region to independently access specific word lines without requiring complex stepped patterning, thereby simplifying manufacturing while maintaining selective access capability.
Solution Approach 2:
The invention transitions from two-dimensional planar patterning to three-dimensional vertical stacking. By forming transistors at different heights in the vertical dimension, the device achieves stepped-like functionality without requiring complex lateral patterning processes, thus reducing manufacturing complexity while enabling word line selection.
2Ease of operation
If pass transistors are formed over the substrate to apply voltage to desired word lines, then voltage can be applied to selected word lines, but the memory device requires additional area and integration degree is limited
Solution Approach 1:
The invention merges the functions of pass transistors and memory cell transistors into a unified structure. The same transistors formed in contact regions serve both as selection switches and as part of the memory cell array, eliminating the need for separate pass transistor regions and thereby reducing overall device area while maintaining voltage application capability.
Solution Approach 2:
The transistors formed in contact regions perform multiple functions: they act as pass transistors for voltage application to word lines, serve as selection transistors for memory operations, and contribute to the overall memory cell structure. This multi-functionality eliminates redundant components and reduces device area.
3Quantity of substance
If the number of stacked word lines is increased to improve integration density, then integration degree increases, but the manufacturing process becomes more complex
Solution Approach 1:
The invention performs preliminary actions by forming all necessary transistors in contact regions before forming the stacked word line structures. The support body is also formed in advance with appropriate height variations. This preliminary configuration enables subsequent simple deposition of conductive layers without requiring complex stepped patterning for each additional word line, thus allowing high integration density with manageable manufacturing complexity.
Data Source
AI summary
A semiconductor device includes a substrate on which a plurality of contact regions are defined, a plurality of transistors formed in the plurality of contact regions, a support body formed over the plurality of transistors and including a top surface, portions of which have different heights in the plurality of contact regions, a plurality of stacked structures including a plurality of conductive layers stacked over the support body, slits located between the plurality of stacked structures, first lines coupled to first junctions of the plurality of transistors through the slits, and second lines coupled to second junctions of the plurality of transistors through the slits.