3D NAND Charge Storage Structure for Word Line Isolation
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Solution Overview
Problem
3D memory devices face issues such as interference between word lines and insufficient programming capabilities.
Innovation Solution
A memory device with a composite stacked structure featuring a channel pillar, charge storage units, tunneling layer, and dual blocking layers is fabricated, where the charge storage units are separated and have increased thickness, reducing word line interference and enhancing programming capability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If charge storage units are made thicker to enhance programming capability, then programming capability is improved, but device area increases
Solution Approach 1:
The patent transitions from planar 2D charge storage to vertical 3D charge storage by forming charge storage units extending in the vertical direction through stacked structures. This dimensional change allows increased charge storage capacity and programming capability without proportionally increasing the planar device area, as the additional storage capacity is achieved by utilizing the vertical dimension rather than expanding horizontally.
Solution Approach 2:
The patent implements nested structures where charge storage units are embedded within stacked structures comprising multiple layers of insulating materials and conductive layers. The charge storage units are positioned within recesses formed in the stacked structure, creating a nested configuration that maximizes the use of available space while maintaining increased charge storage thickness for enhanced programming capability.
2Productivity
If word lines are placed closer together to increase integration density, then integration density is improved, but interference between word lines increases
Solution Approach 1:
The patent introduces blocking layers as intermediary structures between adjacent word lines in the stacked structure. These blocking layers act as mediators that electrically isolate adjacent conductive layers, preventing interference between word lines while allowing the word lines to be placed closer together for increased integration density. The blocking layers are formed in recesses of the stacked structure and provide electrical isolation without requiring increased spacing between word lines.
Solution Approach 2:
The patent segments the conductive layers by introducing blocking layers that divide and isolate adjacent word lines. This segmentation approach allows each word line to be electrically independent while maintaining close proximity for high integration density. The blocking layers create distinct electrical zones that prevent cross-talk and interference between adjacent word lines.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively reduces word line interference and enhances programming capability by increasing the area of charge storage units, leading to improved operational efficiency.
Implementation Method 1
The tunneling layer is disposed between the channel pillar and the plurality of charge storage units
Implementation Method 2
The plurality of charge storage units are embedded in the first stacked structure and located between the channel pillar and the plurality of conductive layers
Data Source
AI summary
A memory device includes a composite stacked structure, a channel pillar, charge storage units, a tunneling layer, and at least one blocking layer. A first stacked structure includes insulating layers and conductive layers stacked alternately over a first region. A second stacked structure includes the insulating layers and intermediate layers alternately stacked over a second region. The charge storage units are embedded in the first stacked structure, and is located between the channel pillar and the conductive layers. The at least one blocking layer is disposed between the charge storage units and the conductive layers. A thickness of one of the plurality of the charge storage units is greater than a thickness of a corresponding conductive layer. The memory device is applicable to 3D NAND flash memory to create memory devices with high capacity and performance.