3D NAND Wordline Access Layout Without Staircase Contacts
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Solution Overview
Problem
Existing 3D NAND memory technologies face challenges in wordline contact formation due to high production costs, yield loss from short-circuits, and limited layout flexibility, exacerbated by the staircase process, which increases die size and congestion as the number of tiers increases.
Innovation Solution
A novel wordline contact structure that eliminates the staircase formation, allowing direct contact from the top of the array to each wordline, with through array vias and wordlines comingled in a shared access structure, reducing process steps and avoiding short-circuits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the staircase process is used to form wordline contacts, then wordline contacts can be formed in existing 3D NAND structures, but production costs increase and yield loss occurs from short-circuits
Solution Approach 1:
The patent extracts and eliminates the staircase formation process from the wordline contact fabrication sequence. By removing this intermediate structural step, the process reduces the number of process steps required, thereby lowering production costs while maintaining reliable electrical connections between wordlines and contacts through direct vertical alignment.
Solution Approach 2:
Instead of forming wordline contacts through the traditional staircase approach that requires multiple etching and filling steps, the patent inverts the methodology by using direct vertical etching through the stacked memory structure. This inverted approach forms contacts that directly reach the wordlines without requiring staircase intermediaries, reducing both cost and short-circuit risks.
2Quantity of substance
If the number of tiers in 3D NAND is increased, then memory capacity is improved, but die size and congestion increase due to more routing paths
Solution Approach 1:
The patent transitions from a two-dimensional planar routing approach to a three-dimensional vertical routing approach. By forming wordline contacts that extend vertically through the stacked memory structure and aligning them with through-array vias in the same lateral footprint, the design accommodates increased memory capacity from additional tiers without proportionally increasing die size, as the routing paths utilize the vertical dimension efficiently.
3Adaptability or versatility
If the staircase process is used, then wordline contacts can be formed, but layout flexibility is limited and die size increases
Solution Approach 1:
The patent merges the wordline contact formation with the through-array via formation into a unified process. Both structures are formed simultaneously using the same etching and filling steps, allowing them to share the same lateral footprint and be positioned flexibly within the array block. This merging eliminates the need for separate staircase structures, thereby increasing layout flexibility and reducing die size.
Data Source
AI summary
Systems, apparatuses, and methods may provide for technology that arranges a wordline access structure for memory devices. The memory device includes a memory array and a memory block coupled to the memory array. The memory block includes a plurality of wordlines penetrating through a plurality of decks of a non-volatile memory structure. A plurality of through array vias penetrate through the plurality of decks, where the plurality of through array vias and the plurality of wordlines are comingled in a shared wordline access structure area. Additionally, or alternatively, the memory device is manufactured based on forming multi-level via holes penetrating through a plurality of decks of a non-volatile memory structure of a memory device based on wordline contact patterning. A metal film is deposited to fill the via holes to form wordline contacts.