3D NAND Word-Line Biasing to Prevent Write Disturb
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
In three-dimensionally stacked semiconductor memory devices, malfunctions such as erroneous writing can occur due to electrons trapped in joints between memory pillars, leading to increased threshold voltages in non-writing-target memory cell transistors.
Innovation Solution
The semiconductor memory device employs a configuration where a first word line is provided above a substrate, a second word line is stacked on the first word line, and a third word line is stacked on the second word line. A first semiconductor layer with a joint between its parts passes through these word lines, and a row decoder applies specific voltages to these word lines during a write operation to manage electron flow and prevent erroneous writing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If a three-dimensionally stacked memory structure is used to increase storage capacity, then the storage density is improved, but electrons trapped in joints between memory pillars cause erroneous writing in non-writing-target memory cell transistors
Solution Approach 1:
The patent applies a pre-charge voltage to the first word line before the write operation to create a potential barrier that prevents electrons trapped in joints from being injected into non-writing-target memory cell transistors. This preliminary action addresses the reliability issue caused by the three-dimensional stacked structure while maintaining its high storage capacity.
Solution Approach 2:
The patent applies different voltages to different word lines during the write operation: a pre-charge voltage to the first word line, a pass voltage to the second word line, and a write voltage to the third word line. This local differentiation of voltage conditions prevents erroneous writing in non-writing-target transistors while enabling successful writing in the target transistor.
2Quantity of substance
If multiple word lines are stacked to form a three-dimensional structure, then the memory device density is improved, but the complexity of voltage control during write operations increases
Solution Approach 1:
The row decoder applies a pre-charge voltage to the first word line before the write operation begins. This preliminary voltage application simplifies the overall control by establishing proper initial conditions that prevent electron injection from joints, reducing the need for complex real-time adjustments during the write operation.
Solution Approach 2:
The patent uses different voltage parameters for different word lines: pre-charge voltage for the first word line, pass voltage for the second word line, and write voltage for the third word line. By changing and optimizing these voltage parameters, the system achieves reliable write operations in a three-dimensional structure without excessive control complexity.
Data Source
AI summary
According to one embodiment, a semiconductor memory device includes the following configuration. A second word line is provided above a first word line on a substrate. A third word line is provided above the second word line. A semiconductor layer includes a first part that passes through the first word line, a second part that passes through the second and the third word lines, and is provided above the first part, and a joint provided between the first and second parts. When a write operation is performed on a memory cell of the third word line, prior to applying a write voltage to the third word line, a first voltage is applied to a bit line, a second voltage is applied to the third word line, and a third voltage higher than the second voltage is applied to the second word line.