3D NAND Word Line Layout With Zigzag Connecting Electrodes
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Solution Overview
Problem
The increasing demand for higher data processing capabilities in electronic devices requires more integrated semiconductor memory devices, which existing technologies struggle to achieve with conventional planar transistor structures, necessitating a shift to vertical transistor structures in memory devices.
Innovation Solution
A memory device design featuring a substrate with stacked gate electrode layers, including unit electrodes and connecting electrodes, where the connecting electrodes are offset to form zigzag patterns, allowing for increased connectivity and integration by forming word lines across multiple unit areas without additional wiring, enhancing the degree of integration and capacity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional planar transistor structures are used, then manufacturing processes are simple, but the degree of integration and capacity of memory devices cannot be increased sufficiently
Solution Approach 1:
The patent transitions from conventional planar (2D) transistor structures to vertical (3D) transistor structures by extending the channel length in the vertical direction perpendicular to the substrate. This dimensional change allows for increased integration density without proportionally increasing the footprint area, thereby resolving the contradiction between integration capacity and structural complexity.
Solution Approach 2:
The patent implements a stacked gate electrode structure where multiple gate electrodes are arranged vertically in layers around the channel. This nested arrangement allows multiple control elements to be packed into a compact vertical space, enabling higher integration while maintaining manageable structural complexity through systematic layering.
2Productivity
If the number of word lines is increased to improve capacity, then more wiring is required, but this increases device complexity and manufacturing difficulty
Solution Approach 1:
The patent arranges word lines in a three-dimensional stacked configuration rather than spreading them out in a single plane. By extending the word line structure vertically across multiple layers, the design increases memory capacity through additional addressable lines without proportionally increasing the lateral wiring complexity, as multiple word lines share the same footprint area through vertical stacking.
Data Source
AI summary
A memory device includes gate electrode layers stacked on an upper surface of a substrate and each including a plurality of unit electrodes extending in a first direction, and a plurality of connecting electrodes connecting the unit electrodes to each other. The memory device also includes channel structures extending through the gate electrode layers in a direction perpendicular to the upper surface of the substrate, first common source lines extending in the first direction and interposed between the unit electrodes, and second common source lines extending in the first direction between the first common source lines and each having a first line and a second line separated from each other in the first direction by the connecting electrodes.