3D Nanoribbon DRAM Layout for Higher Memory Density
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional memory technologies face challenges in increasing memory density due to limitations in the number of transistors that can be formed on a semiconductor substrate, leading to diminishing returns and increased complexity and cost in scaling memory devices.
Innovation Solution
The use of vertically-stacked nanoribbon-based transistors in advanced CMOS processes allows for higher density embedded memory by moving access transistors to back-end-of-line layers, enabling independent gate control and thicker interlayer dielectrics, which increases capacitance and reduces footprint area, while embedding capacitors in upper metal layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If conventional planar transistors are used in memory devices, then manufacturing process is simpler, but memory density is limited due to substrate area constraints
Solution Approach 1:
The patent transitions from planar two-dimensional transistor布局 to three-dimensional vertically-stacked nanoribbon transistors. Multiple nanoribbons are stacked vertically with each having independent gate control, enabling memory cells to be arranged in three dimensions rather than confined to a planar substrate, thereby dramatically increasing memory density without proportionally increasing substrate area
Solution Approach 2:
The memory device is segmented into multiple vertically-stacked nanoribbon transistors (first, second, third, and fourth nanoribbons) that can be independently controlled via separate gates. This segmentation allows each nanoribbon to function as an independent access transistor, enabling complex memory operations and higher density while maintaining manufacturability through modular fabrication processes
2Quantity of substance
If more transistors are packed on substrate to increase density, then memory capacity increases, but manufacturing complexity and cost increase
Solution Approach 1:
By stacking nanoribbons vertically in the z-dimension rather than packing them horizontally on the substrate plane, the invention achieves higher transistor counts without increasing lateral manufacturing complexity. The vertical stacking allows standard planar fabrication processes to be extended into three dimensions, maintaining ease of manufacture while dramatically increasing the number of transistors per substrate area
Solution Approach 2:
The vertically-stacked nanoribbon structure serves multiple functions: each nanoribbon acts as an access transistor with independent gate control, the stack enables capacitor coupling between layers, and the configuration supports both read and write operations. This multi-functionality reduces the need for separate dedicated structures, simplifying manufacturing while achieving high transistor density
3Reliability
If access transistors are moved to back-end-of-line layers, then independent gate control is enabled and capacitance increases, but manufacturing process becomes more complex
Solution Approach 1:
Moving access transistors from front-end planar layers to back-end vertical stacks enables independent gate control for each nanoribbon in the stack. The vertical arrangement in back-end-of-line layers allows gates to be positioned around each nanoribbon, providing independent control that improves reliability while the modular nature of the stacking process keeps manufacturing complexity manageable
Solution Approach 2:
The vertically-stacked nanoribbon structure acts as an intermediary that enables independent gate control without requiring complex routing and interconnection schemes. Each nanoribbon in the stack can be controlled by its own gate, and the stack configuration naturally provides the necessary isolation and control pathways, simplifying the overall manufacturing process compared to alternative approaches
4Reliability
If capacitor thickness is increased to increase capacitance, then memory performance improves, but substrate area occupied increases
Solution Approach 1:
The patent increases capacitance by stacking capacitors vertically in three dimensions rather than increasing the lateral area of planar capacitors. Multiple capacitor structures are arranged in vertical layers, allowing significant capacitance enhancement while maintaining a compact footprint on the substrate. This vertical stacking enables high capacitance values without proportionally increasing the device footprint
Data Source
AI summary
Described herein are IC devices that include semiconductor nanoribbons stacked over one another to realize high-density three-dimensional (3D) dynamic random-access memory (DRAM). An example device includes a first semiconductor nanoribbon, a second semiconductor nanoribbon, a first source or drain (S/D) region and a second S/D region in each of the first and second nanoribbons, a first gate stack at least partially surrounding a portion of the first nanoribbon between the first and second S/D regions in the first nanoribbon, and a second gate stack, not electrically coupled to the first gate stack, at least partially surrounding a portion of the second nanoribbon between the first and second S/D regions in the second nanoribbon. The device further includes a bitline coupled to the first S/D regions of both the first and second nanoribbons.