3D Nanosheet 2D Material Stack for Higher-Density Transistors
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional semiconductor device fabrication techniques are limited by their two-dimensional nature, which restricts transistor density and complexity, approaching physical atomic limitations with single-digit nanometer nodes, necessitating a shift to more complex and dimensional semiconductor circuits.
Innovation Solution
The integration of 2D materials with 3D nanosheet structures to form semiconductor devices, allowing for increased transistor density in volume rather than area, using nanosheet masks to create precise openings and deposits for high-mobility 2D materials, enabling sub-nanometer channel thickness regions and improved performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If 2D fabrication techniques are used to manufacture transistors, then transistor density per unit area can be increased through scaling, but the devices approach physical atomic limitations with single digit nanometer nodes and lack complexity and dimensionality
Solution Approach 1:
The patent transitions from 2D planar fabrication to 3D vertical stacking by forming multiple semiconductor layers (e.g., SiGe and Si layers) stacked vertically to create nanosheet channels. This dimensional change allows transistors to be stacked in the vertical direction, increasing device density while maintaining manufacturability and enabling more complex 3D circuit architectures that overcome the limitations of single-digit nanometer 2D scaling.
2Quantity of substance
If single digit nanometer scaling is pursued in 2D circuits, then transistor density increases, but physical atomic limitations are approached making further scaling difficult
Solution Approach 1:
Instead of continuing to scale lateral dimensions to single-digit nanometers where atomic precision is required, the patent stacks multiple semiconductor layers vertically to form 3D nanosheets. This approach increases transistor density by utilizing the vertical dimension, thereby avoiding the need for extremely precise single-digit nanometer lateral patterning and reducing the impact of atomic-scale manufacturing variations.
Solution Approach 2:
The patent divides the semiconductor structure into multiple discrete layers (e.g., alternating SiGe and Si layers) that are formed separately and then stacked. This segmentation allows each layer to be manufactured with relaxed precision requirements, and the final high-density structure emerges from the vertical stacking of these individually manufactured layers, avoiding the need for single-step atomic-precision fabrication.
Data Source
AI summary
Methods for the manufacture of semiconductor devices constructed with two-dimensional (2D) materials and conductive oxides using three-dimensional (3D) nanosheets are disclosed. Aspects can include forming the stack of layers comprising a first layer of a semiconductive-behaving material separated from a base layer by a first layer of a first dielectric material and a first layer of a second dielectric material; a second layer of the semiconductive-behaving material separated from the first layer of the semiconductive-behaving material by a second layer of the second dielectric material; and a second layer of the second dielectric material formed on the second layer of the semiconductive-behaving material. Aspects include forming a metal contact coupled with the semiconductive-behaving material, forming a 2D material on the semiconductive-behaving material, forming a layer of a high-k dielectric material on the 2D material, and forming a gate metal on the high-k dielectric material.