3D Nanosheet Architecture Using 2D Materials for Transistor Density
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Solution Overview
Problem
Conventional semiconductor device fabrication techniques are limited by their two-dimensional nature, which restricts transistor density and complexity, approaching physical atomic limitations as they attempt to scale down to single-digit nanometer nodes.
Innovation Solution
The integration of conductive oxide and 2D materials to form advanced 3D device architectures using nanosheets, allowing for increased transistor density by forming sub-nanometer channel thickness regions and enabling precise deposition of materials for high-performance transistors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If conventional 2D fabrication techniques are used to scale down to single-digit nanometer nodes, then transistor density per unit area increases, but physical atomic limitations are approached and manufacturing precision deteriorates
Solution Approach 1:
The patent transitions from conventional 2D planar fabrication to 3D vertical stacking architecture. Multiple transistor layers are stacked vertically to increase density, moving the problem from two-dimensional scaling limits to three-dimensional space utilization. This allows continued density improvement without further reducing lateral dimensions to atomic limits.
Solution Approach 2:
The patent implements nested structures where gate electrodes, channel layers, and dielectric materials are arranged in concentric or layered configurations. The gate wraps around the channel in FinFET or GAA structures, creating nested geometries that improve control and packing efficiency beyond planar layouts.
2Ease of manufacture
If 2D fabrication techniques are used, then manufacturing processes remain simple, but device complexity and transistor dimensionality are limited
Solution Approach 1:
The patent divides the transistor structure into distinct functional segments: source/drain regions, channel regions, gate electrodes, and dielectric layers. Each segment is formed through separate fabrication steps, allowing independent optimization and control of each component's properties while maintaining overall device functionality.
Solution Approach 2:
The patent introduces vertical stacking to create three-dimensional transistor architectures, increasing device complexity and dimensionality from 2D planar to 3D vertical structures, enabling higher density and improved performance.
3Reliability
If sub-nanometer channel thickness regions are formed using 2D materials, then transistor performance improves, but manufacturing precision requirements increase
Solution Approach 1:
The patent changes the material parameter from conventional semiconductors to 2D materials (such as MoS2, WS2, WSe2) which naturally form atomically thin layers. This material substitution enables precise thickness control at the atomic level, achieving sub-nanometer channel thickness with inherent precision that conventional materials cannot provide.
Solution Approach 2:
The patent replaces mechanical thickness control methods (such as physical vapor deposition or chemical vapor deposition thickness control) with material-intrinsic thickness determination. 2D materials are synthesized with predetermined atomic layer thickness, eliminating the need for complex mechanical thickness control during fabrication.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances transistor density and complexity, overcoming scaling limitations and enabling the creation of high-performance semiconductor devices suitable for various logical circuits, including CPUs, GPUs, and FPGAs, with improved electrical connections and robust performance.
Implementation Method 1
selectively forming the 2D material around the conductive oxide layer
Implementation Method 2
selectively forming the 2D material around the conductive oxide layer
Data Source
AI summary
Methods for the manufacture of semiconductor devices constructed advanced three-dimensional (3D) device architectures using nanosheets with two-dimensional (2D) materials are disclosed. Aspects can include forming a dielectric layer; forming a conductive oxide layer on the dielectric layer; selectively forming a two-dimensional (2D) material around the conductive oxide layer; forming an active gate around the 2D material; and forming a first metal structure and a second metal structure, wherein the dielectric layer and conductive oxide layer extend between the first metal structure and the second metal structure.