3D Nano Sheet Transistor Architecture for HV LV Co-Integration
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Solution Overview
Problem
The challenge in semiconductor device fabrication is the limitations of two-dimensional (2D) circuits as scaling reaches single-digit nanometer nodes, prompting a need for three-dimensional (3D) semiconductor circuits where transistors are stacked, and the integration of high voltage (HV) and low voltage (LV) devices on the same substrate without compromising performance or increasing complexity.
Innovation Solution
The approach involves forming semiconductor devices with a first field effect transistor and a stack of field effect transistors using nano sheets, where the first transistor has a common gate metal and the stack has gate-all-around metal, utilizing an epitaxial stack of materials like Si, SiGe, and SiGe2, allowing for the co-integration of HV and LV devices on the same substrate with flexible transistor width and length, enabling robust drive currents and high performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If transistors are stacked in 3D configuration, then transistor density is improved, but device complexity increases
Solution Approach 1:
The patent transitions from traditional 2D planar transistor arrangements to 3D vertical stacking configurations. Multiple transistor channels are stacked vertically along the growth direction of the epitaxial layers, enabling higher transistor density by utilizing the third dimension (vertical direction) rather than only the planar dimensions.
Solution Approach 2:
The epitaxial stack is divided into multiple discrete transistor channels, each with its own source and drain regions. The stack is segmented into individual functional units that can be independently controlled by gate electrodes, allowing each channel to operate as a separate transistor while maintaining a unified vertical structure.
2Adaptability or versatility
If HV and LV devices are integrated on the same substrate, then device versatility is improved, but manufacturing precision requirements increase
Solution Approach 1:
Different regions of the epitaxial stack are engineered with distinct material compositions and doping profiles to create local variations in electrical properties. High voltage devices utilize regions with wider bandgap materials (such as SiC or GaN) while low voltage devices use regions with different material characteristics, allowing both device types to coexist on the same substrate with optimized performance for their respective voltage requirements.
Solution Approach 2:
The epitaxial growth process is designed to create a universal platform that can accommodate both high voltage and low voltage device configurations. The same fundamental growth techniques and material systems are used to form both types of devices, enabling a single fabrication process flow to produce multi-functional integrated circuits with different voltage requirements.
3Reliability
If nano sheets with varying lengths are used, then transistor performance is improved, but process complexity increases
Solution Approach 1:
The epitaxial growth process is designed to pre-form nano sheets with different lengths directly during the material deposition phase. By controlling growth parameters and layer thicknesses during epitaxial formation, transistor channels with varying effective lengths are created in advance, eliminating the need for subsequent complex patterning or etching steps to achieve different channel lengths.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method enables the production of high-density 3D circuits with unified architectural design for both HV and LV devices, facilitating maximum 3D logic and memory integration while maintaining performance and reducing costs, with the ability to form transistors of varying sizes and channel lengths without process flow restrictions.
Implementation Method 1
A layer stack of alternating epitaxial materials can includes one or more layers. The layer stack of alternating epitaxial materials can be divided into a first region of nano sheets and a second region of nano sheets
Data Source
AI summary
A method of forming a semiconductor device is presented. A layer stack of alternating epitaxial materials including one or more layers is formed. The layer stack of alternating epitaxial materials into a first region of nano sheets and a second region of nano sheets is divided. A first field effect transistor on a working surface of a substrate using the nano sheets in the first region of nano sheets is formed. A stack of field effect transistors on the working surface of the substrate using the nano sheets in the second region of nano sheets is formed.