3D Nanosheet Memory Cell Structure for Lower Parasitic Capacitance
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Solution Overview
Problem
Existing semiconductor technologies face challenges in achieving high memory cell density and reducing parasitic capacitance in three-dimensional memory devices.
Innovation Solution
A semiconductor device with vertical and horizontal arrangements of nano sheets, including protruding and tapered sheets, surrounded by conductive lines and supported by dielectric layers, along with data storage elements, is fabricated using a method involving mold layer formation, sacrificial isolation layer replacement, and conductive line arrangement.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If three-dimensional memory structure is implemented, then memory cell density is improved, but parasitic capacitance increases
Solution Approach 1:
The patent implements a three-dimensional memory structure where memory cells are stacked vertically across multiple layers (first through fourth memory cell layers). This vertical stacking in the third dimension dramatically increases memory cell density without proportionally increasing parasitic capacitance, as the 3D architecture optimizes spatial utilization while maintaining electrical performance through careful design of conductive lines and isolation structures.
2Quantity of substance
If memory cell density is increased, then storage capacity is improved, but device complexity increases
Solution Approach 1:
The memory device is segmented into multiple distinct layers (first, second, third, and fourth memory cell layers), each containing memory cells with specific configurations. This segmentation allows for modular design and manufacturing, where each layer can be independently optimized and processed, thereby managing device complexity while achieving high overall density through vertical stacking.
Solution Approach 2:
By transitioning from a planar two-dimensional layout to a three-dimensional vertical stacking architecture, the patent achieves high memory cell density without proportionally increasing in-plane device complexity. The vertical dimension provides additional storage capacity while maintaining manageable complexity through standardized layer repetition and systematic inter-layer connectivity.
3Ease of manufacture
If conventional planar memory structure is used, then manufacturing is simpler, but memory cell density is limited
Solution Approach 1:
The patent employs a three-dimensional vertical stacking architecture with multiple memory cell layers arranged along the vertical direction, fundamentally moving from conventional planar two-dimensional memory structures. This dimensional transition enables dramatically higher memory cell density by utilizing vertical space, while the modular layer-by-layer construction approach maintains manufacturing feasibility through systematic process repetition.
Solution Approach 2:
The manufacturing process utilizes preliminary patterning and layer formation steps where sacrificial layers are first formed, then memory cell structures are built around them, and finally the sacrificial layers are removed. This preliminary action approach simplifies the complex 3D manufacturing process by breaking it into manageable sequential steps, making the vertical stacking architecture manufacturable.
Data Source
AI summary
A semiconductor device including high-integrated memory cells and a method for fabricating the semiconductor device are provided. The semiconductor device includes vertical and horizontal arrangements of nano sheets including horizontal sheets, which include protruding sheet nodes, and tapered sheets, which are continuous in a first horizontal direction from the horizontal sheets, a vertical arrangement of first conductive lines that surround portions of the horizontal sheets in the horizontal arrangement and are oriented in a second horizontal direction, first contact nodes covering the protruding sheet nodes of the horizontal sheets, a horizontal arrangement of second conductive lines that cover the first contact nodes and are oriented in a vertical direction, supporters that are disposed between the second conductive lines in the horizontal arrangement and are oriented in the vertical direction, and data storage elements coupled to the tapered sheets.