3D Nanosheet Memory Cell Layout for Higher Integration Density
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Solution Overview
Problem
The integration of two-dimensional (2D) semiconductor devices is limited by the high cost and complexity of ultra-high-priced equipment required for miniaturization, necessitating the development of three-dimensional (3D) memory devices to enhance integration density.
Innovation Solution
The implementation of 3D memory cells and devices with vertically oriented bit lines, nanosheet transistors, and capacitors, along with a gate-all-around word line structure, allows for increased integration by stacking transistors and capacitors on a substrate, enabling a higher degree of packing density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If 2D semiconductor devices are used, then manufacturing process is simpler, but integration density is limited
Solution Approach 1:
The patent transitions from two-dimensional planar memory cell layout to three-dimensional vertical stacking architecture. Multiple memory cells are stacked vertically along the third dimension, with bit lines extending vertically through the stack and word lines wrapping around nanosheet channels in a gate-all-around configuration. This dimensional change enables significantly higher integration density while maintaining manufacturing feasibility through established semiconductor fabrication processes.
2Quantity of substance
If pattern miniaturization is pursued, then integration density increases, but equipment cost and complexity increase
Solution Approach 1:
Instead of continuing to miniaturize patterns in the planar direction which requires increasingly complex and expensive equipment, the patent stacks memory cells vertically to achieve higher integration density using existing fabrication capabilities. The vertical stacking approach bypasses the need for ultra-high-priced equipment while still increasing the quantity of functional elements.
Solution Approach 2:
The memory device is segmented into multiple discrete memory cell stacks that can be independently formed and then combined. Each stack contains separated functional elements (bit line, nanosheet channels, word lines, capacitors) that are fabricated in distinct process steps and then integrated vertically, allowing for manageable manufacturing complexity.
3Quantity of substance
If vertical stacking is implemented, then integration density increases, but electrical shielding between cells becomes more challenging
Solution Approach 1:
The word lines are configured to wrap completely around the nanosheet channels in a gate-all-around structure, creating nested concentric arrangements. This nesting provides effective electrical shielding and isolation between adjacent memory cells in the vertical stack, preventing harmful electrical interference while maintaining compact geometry.
Solution Approach 2:
Insulating layers and dielectric materials are introduced as intermediary elements between adjacent conductive components in the vertical stack. These intermediary layers provide electrical isolation and shielding between neighboring cells, preventing cross-talk and interference while allowing the memory cells to be densely packed vertically.
Data Source
AI summary
A memory cell comprising a substrate, a bit line vertically oriented from the substrate along a first direction, a nanosheet transistor including at least one nanosheet horizontally oriented from the bit line along a second direction perpendicular to the first direction, and a capacitor horizontally oriented from the nanosheet transistor along the second direction.