3D Nano-Sheet Transistor Stacks for Higher Density Logic Layouts
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Solution Overview
Problem
The challenge in semiconductor device fabrication is to increase transistor density beyond the limitations of two-dimensional circuits, particularly in scaling to single-digit nanometer nodes, where traditional 2D transistors face difficulties in packing more devices per unit area, and 3D integration for logic chips is complex.
Innovation Solution
The use of multiple selective nano-sheets for fabricating 3D transistors in different device regions, enabling strategic layout optimization for multi-dimensional CMOS logic circuits with vertical stacking and side-by-side building blocks, allowing for efficient Idsat and flexible FET combinations, including the fabrication of tunneling field effect transistors without additional process steps.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If traditional 2D transistors are used for scaling, then manufacturing process is simple, but transistor density per unit area is limited
Solution Approach 1:
The patent transitions from 2D planar transistors to 3D vertically-stacked transistors, stacking multiple transistor layers in the vertical dimension to increase transistor density per unit area. This dimensional change allows more transistors to be packed into the same footprint by utilizing the third dimension (height) rather than only expanding in the planar dimensions.
Solution Approach 2:
The fabrication process is segmented into distinct stages: forming alternating semiconductor layers (e.g., Si/SiGe), creating sacrificial nanowire templates, depositing gate materials, and selectively removing sacrificial layers. This segmentation allows complex 3D structures to be built through a series of manageable, modular process steps rather than a single complex operation.
2Quantity of substance
If 3D integration is implemented for logic chips, then transistor density is increased, but device fabrication complexity increases substantially
Solution Approach 1:
Multiple transistor types (NFET and PFET) are merged into a single integrated fabrication process using alternating semiconductor layers with different bandgaps. The process combines layer formation, gate deposition, and selective etching into a unified flow that simultaneously creates both NFET and PFET devices, reducing the need for separate processing lines.
Solution Approach 2:
The patent utilizes changes in material parameters (bandgap energy, etch selectivity) to enable selective processing. By alternating between materials with different properties (e.g., Si with narrow bandgap and SiGe with wider bandgap), the process can selectively form NFET channels in one layer while forming PFET channels in another layer using the same fabrication steps.
3Productivity
If more FET combinations are used for circuit optimization, then circuit performance is improved, but layout complexity increases
Solution Approach 1:
The alternating layer structure serves multiple functions simultaneously: it provides mechanical support, defines electrical isolation regions, creates selective channel formation zones for different transistor types, and enables varied circuit configurations. This multi-functionality reduces layout complexity by consolidating multiple structural roles into a single architectural framework.
Data Source
AI summary
A semiconductor device includes a plurality of nano-channel field-effect transistor stacks positioned adjacent to each other such that source-drain regions are shared between adjacent nano-channel field-effect transistor stacks, each nano-channel field-effect transistor stack including at least two nano-channel field-effect transistors and corresponding source/drain regions vertically separated from each other.