3D Neural Network Array with Programmable Synapses
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Solution Overview
Problem
Conventional neural network arrays face limitations in density and functionality due to CPU bottlenecks in software implementations and circuit size constraints in hardware implementations, which hinder real-time performance and configurability.
Innovation Solution
A configurable three-dimensional neural network array is developed, featuring interconnected network layers with programmable resistive synapse elements and select transistors that eliminate the need for operational amplifiers or comparators, allowing for flexible configuration and high-density neural network design.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If software implementation using CPU is used, then neural network learning capabilities are achieved, but processing speed becomes a bottleneck for real-time tasks
Solution Approach 1:
The patent replaces the mechanical/CPU-based software execution system with a hardware-based neural network array that directly performs neural network operations through electrical signal processing. The array uses interconnected neurons and synapses implemented as physical circuit elements (transistors, resistors, capacitors) to execute neural network computations in parallel, eliminating the sequential processing bottleneck of CPU-based software implementations.
Solution Approach 2:
The patent transitions from two-dimensional planar circuit layouts to three-dimensional stacked neural network arrays. Multiple neural network layers are stacked vertically with through-silicon vias connecting corresponding neurons across layers, enabling massive parallel processing and significantly increasing the number of neurons and synapses that can be implemented in a given footprint, thereby achieving both high speed and high density.
2Speed
If hardware implementation is used, then processing speed is improved, but circuit size limits the density and functionality of the neural network
Solution Approach 1:
The patent employs three-dimensional stacking of neural network layers to increase density. Multiple layers of neurons are stacked vertically with through-silicon vias providing vertical interconnections, allowing the neural network array to achieve high neuron counts and functionality without proportionally increasing the lateral circuit footprint, thus maintaining speed while reducing effective circuit size.
Solution Approach 2:
The patent merges multiple functions into single circuit elements. Select transistors serve dual purposes as both row/column selection devices and as part of the neural network computation path. Through-silicon vias simultaneously provide mechanical support and electrical interconnection between stacked layers. This functional integration reduces the overall circuit complexity and size while maintaining processing speed.
3Reliability
If operational amplifiers and comparators are used to connect output neurons to select gates, then signal processing is achieved, but circuit density is reduced
Solution Approach 1:
The patent extracts and removes the operational amplifiers and comparators from the neural network array architecture. Instead of using these discrete signal processing components, the design relies on the inherent electrical properties of the transistor-based neural network elements and passive RC time constants to perform signal integration and thresholding functions, thereby eliminating bulky components and increasing circuit density.
Solution Approach 2:
The patent implements self-service signal processing where the neural network elements themselves perform the processing functions previously requiring external components. The synapse circuits naturally integrate incoming signals through their RC time constants, and the select transistor gate thresholds automatically perform comparison functions, eliminating the need for separate operational amplifiers and comparators while maintaining signal processing reliability.
4Ease of manufacture
If fixed neural network arrays are used, then manufacturing is simplified, but configurability for different tasks is limited
Solution Approach 1:
The patent implements dynamic configurability through programmable synapse weights and selectable neural network paths. The synapse resistances can be programmed to different values to encode different weight values for different neural network tasks. Additionally, select transistors can be enabled or disabled to reconfigure the active neural network topology, allowing the same physical array to adapt to different neural network architectures and functions while maintaining manufacturing simplicity through standard semiconductor fabrication processes.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution enables fast and compact neural network arrays with enhanced configurability, allowing any number of neurons to be configured for specific tasks and enabling easy subdivision of array structures, thereby overcoming the limitations of conventional arrays.
Implementation Method 1
Each synapse element includes a programmable resistive element
Implementation Method 2
select transistors connected between the synapse lines and the output neurons. Gate terminals of the select transistors receive input signals
Data Source
AI summary
Configurable three-dimensional neural network array. In an exemplary embodiment, a three-dimensional (3D) neural network array includes a plurality of stacked synapse layers having a first orientation, and a plurality of synapse lines having a second orientation and passing through the synapse layers. The neural network array also includes synapse elements connected between the synapse layers and synapse lines. Each synapse element includes a programmable resistive element. The neural network array also includes a plurality of output neurons, and a plurality of select transistors connected between the synapse lines and the output neurons. The gate terminals of the select transistors receive input signals.