3D Stacked Neural Network Architecture for Lower Power and Smaller Footprint
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing artificial neural network hardware implementations face challenges in reducing power consumption and miniaturization due to the need for multiple elements per neuron and synapse, leading to increased size and resource requirements.
Innovation Solution
A stackable 3D artificial neural network device is designed with a substrate featuring a neuron block and a synapse block, where the blocks are electrically connected through coupling elements, minimizing signal transmission pathways and allowing simultaneous manufacturing on a single surface, thereby reducing power consumption and size.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple elements are used for one neuron and one synapse in traditional ANN hardware, then the computing function and signal transmission are achieved, but the device size and power consumption increase significantly
Solution Approach 1:
The patent merges multiple functional elements (neurons and synapses) into a unified 3D stacked architecture where channel elements serve dual purposes for both neuronal computation and synaptic signal transmission. This consolidation reduces the total number of discrete components needed while maintaining full ANN functionality.
Solution Approach 2:
The patent transitions from a planar 2D layout to a three-dimensional stacked architecture, arranging channel elements vertically across multiple layers. This dimensional change enables compact integration of neuron and synapse blocks, dramatically reducing device footprint while preserving all necessary computational functions.
2Reliability
If multiple elements are used for one neuron and one synapse in traditional ANN hardware, then the computing function and signal transmission are achieved, but power consumption increases
Solution Approach 1:
The patent merges multiple functional elements (neurons and synapses) into a unified 3D stacked architecture where channel elements serve dual purposes for both neuronal computation and synaptic signal transmission. This consolidation reduces the total number of discrete components needed while maintaining full ANN functionality.
Solution Approach 2:
The patent transitions from a planar 2D layout to a three-dimensional stacked architecture, arranging channel elements vertically across multiple layers. This dimensional change enables compact integration of neuron and synapse blocks, dramatically reducing device footprint while preserving all necessary computational functions.
3Volume of moving object
If neuron block and synapse block are stacked together on single substrate with minimized signal transmission pathway, then power consumption is reduced and size is minimized, but manufacturing complexity increases
Solution Approach 1:
The patent segments the ANN device into distinct functional blocks (neuron blocks and synapse blocks) that can be independently designed and manufactured. These modular segments are then stacked in a standardized 3D configuration, making the complex structure manageable through systematic division into repeatable units.
Solution Approach 2:
The patent employs universal coupling elements and standardized interface structures that work across all neuron and synapse blocks. This multi-functional design allows the same coupling mechanism to handle various signal types and connections, simplifying the overall manufacturing process despite the 3D stacked complexity.
Data Source
AI summary
Various embodiments relate to a stackable 3D artificial neural network device and a manufacturing method thereof. According to various embodiments, a device is manufactured to include a substrate, a neuron block placed on some areas on one side of the substrate, a synapse block placed on the rest of the areas on one side of the substrate, and the neuron block and the synapse block may include at least one first channel element arranged on one side of the substrate and at least one second channel element stacked on the first channel element.