3D Stacked Neuromorphic Circuit for High-Capacity Interlayer Connectivity
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Solution Overview
Problem
Current semiconductor devices fail to effectively emulate the high-performance, multiple input and output connections of the human nervous system, limiting their capacity and efficiency in neuromorphic computations.
Innovation Solution
A three-dimensional stack structure for semiconductor devices is implemented, featuring synaptic cores, routers, and interconnects that allow for efficient information transfer between layers via through-silicon vias (TSVs), mimicking the brain's neural and synapse circuits and reducing the need for multiple chips and chip-to-chip connections.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If multiple chips and chip-to-chip connections are used to achieve high-performance neuromorphic computations, then the computational capacity and connectivity are improved, but the system size and power consumption increase
Solution Approach 1:
The patent combines multiple functional components (synaptic cores, routers, and interconnects) into a single integrated 3D stacked neuromorphic chip. This merging eliminates the need for multiple separate chips and their interconnections, thereby reducing system size while maintaining high computational capacity through vertical integration.
Solution Approach 2:
The patent transitions from a 2D planar layout to a 3D stacked architecture. By stacking synaptic cores, routers, and interconnects in multiple layers vertically, the system achieves high connectivity and computational capacity without increasing the horizontal footprint, thus reducing overall system size.
2Adaptability or versatility
If multiple chips and chip-to-chip connections are used to achieve high-performance neuromorphic computations, then the computational capacity and connectivity are improved, but the power consumption increases
Solution Approach 1:
The patent combines multiple functional components (synaptic cores, routers, and interconnects) into a single integrated 3D stacked neuromorphic chip. This merging eliminates the need for multiple separate chips and their interconnections, thereby reducing system size while maintaining high computational capacity through vertical integration.
Solution Approach 2:
The patent transitions from a 2D planar layout to a 3D stacked architecture. By stacking synaptic cores, routers, and interconnects in multiple layers vertically, the system achieves high connectivity and computational capacity without increasing the horizontal footprint, thus reducing overall system size.
3Volume of moving object
If a three-dimensional stack structure is implemented to reduce system size, then the volume is reduced, but the manufacturing complexity increases
Solution Approach 1:
The patent divides the neuromorphic system into distinct functional layers (synaptic core layers, router layers, and interconnect layers) that can be manufactured separately and then stacked. This segmentation allows each layer to be optimized and manufactured independently, reducing the overall manufacturing complexity compared to creating a monolithic 3D structure.
Solution Approach 2:
The patent transitions from a 2D planar layout to a 3D stacked architecture. By stacking synaptic cores, routers, and interconnects in multiple layers vertically, the system achieves high connectivity and computational capacity without increasing the horizontal footprint, thus reducing overall system size.
4Adaptability or versatility
If through-silicon vias are used to connect layers, then the inter-layer connectivity is improved, but the manufacturing precision requirements increase
Solution Approach 1:
The patent divides the neuromorphic system into distinct functional layers (synaptic core layers, router layers, and interconnect layers) that can be manufactured separately and then stacked. This segmentation allows each layer to be optimized and manufactured independently, reducing the overall manufacturing complexity compared to creating a monolithic 3D structure.
Data Source
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AI summary
Provided are a neuromorphic circuit having a three-dimensional stack structure and a semiconductor device including the neuromorphic circuit. The semiconductor device includes a first semiconductor layer including one or more synaptic cores, each synaptic core including neural circuits arranged to perform neuromorphic computation. A second semiconductor layer is stacked on the first semiconductor layer and includes an interconnect forming a physical transfer path between synaptic cores. A third semiconductor layer is stacked on the second semiconductor layer and includes one or more synaptic cores. At least one through electrode is formed, through which information is transferred between the first through third semiconductor layers. Information from a first synaptic core in the first semiconductor layer is transferred to a second synaptic core in the third semiconductor layer via the one of more through electrodes and an interconnect of the second semiconductor layer.