3D NoC Interconnect With Segmented Inter-Die Drivers
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Solution Overview
Problem
Extending a network-on-chip (NoC) interconnect across multiple stacked IC dice in 3D IC devices presents timing and signal strength issues, challenging further reductions in IC device sizes and performance improvements.
Innovation Solution
Implementing inter-die buses with driver circuits that interface between vertically-stacked IC dice, utilizing synchronous and asynchronous communication protocols to enhance NoC interconnects, including bi-directional and unidirectional communication paths, and configurable bandwidth to optimize routing and resource efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If NoC interconnect is extended across multiple stacked IC dice in 3D, then communication capability and bandwidth are improved, but timing issues and signal strength degradation occur
Solution Approach 1:
The interconnect system is segmented into multiple segments with dedicated driver circuits at each segment boundary. This segmentation allows each driver to manage signal strength locally, preventing degradation over the extended 3D path while maintaining communication capability across multiple dice.
Solution Approach 2:
Dedicated driver circuits are introduced as intermediary components between the NoC packet switch and the interconnect segments. These drivers act as mediators that actively manage signal strength and timing, compensating for the degradation that occurs when extending interconnect across multiple stacked dice.
2Area of stationary object
If 3D stacked IC dice are used to reduce device size, then integration density is improved, but interconnect complexity and signal integrity issues worsen
Solution Approach 1:
The patent transitions from 2D planar interconnect to 3D vertical interconnect by stacking IC dice. This dimensional change enables compact device packaging while providing additional routing dimensions that reduce interconnect complexity through better spatial distribution of signals.
Solution Approach 2:
The 3D interconnect is divided into discrete segments with dedicated drivers at each boundary. This segmentation manages the complexity by localizing signal integrity challenges to specific segments rather than treating the entire 3D interconnect as a single complex path.
3Reliability
If synchronous communication protocol is used for inter-die bus, then timing control is improved, but adaptability to asynchronous NoC operations deteriorates
Solution Approach 1:
The driver circuit serves as an intermediary that bridges synchronous and asynchronous domains. It receives asynchronous NoC operations and converts them to synchronous signals for the inter-die bus, enabling timing control while maintaining adaptability to various communication protocols.
Solution Approach 2:
The communication system dynamically adapts between synchronous and asynchronous modes depending on the operational requirements. The driver circuit can operate in different modes to accommodate both synchronous timing-critical paths and asynchronous protocol requirements.
Data Source
AI summary
Embodiments herein describe techniques to extend a network-on-chip (NoC) across multiple IC dice in 3D. An integrated circuit (IC) device includes first and second vertically-stacked IC dice, and an inter-die bus that interfaces between the second die and a NoC packet switch (NPS) of the first die. The inter-die bus may include one or more driver circuits coupled to inter-die links of the inter-die bus. Communications over the inter-die links may be synchronous (e.g., packet-based) or asynchronous with the NPS (e.g., based on a point-to-point protocol, such as an AXI protocol). The inter-die bus may interface with a circuit block of the second IC device via a point-to-point (e.g., AXI) protocol or via a NPS of the second IC die. The IC device may include multiple inter-die buses, which may expand inter-die and intra-die routing options.