3D NOR Memory Array Layout for Fine-Pitch Isolation and Etching
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Solution Overview
Problem
In high-density 3-dimensional memory structures, the increasing trench aspect ratio makes etching difficult and costly as memory cell size decreases, limiting the ability to increase memory cell density without compromising manufacturing yield.
Innovation Solution
The introduction of a strong dielectric barrier film between adjacent memory cells and staggering memory cells to improve isolation, along with a two-step deposition of charge-trapping layers to reduce the aspect ratio of trenches and enhance memory cell density, allowing for the formation of memory structures with minute feature sizes and multiple layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory cell size is decreased to increase memory cell density, then memory cell density increases, but trench aspect ratio increases making etching difficult and costly
Solution Approach 1:
The patent transitions from planar 2D memory cell arrangement to 3D vertical stacking architecture. By introducing vertical trenches and stacking memory cells in the third dimension, the patent achieves higher memory cell density without proportionally increasing trench aspect ratio, as the vertical dimension provides additional space for cell placement while maintaining manageable etch depths through careful structural design.
Solution Approach 2:
The patent divides the memory structure into segmented vertical trenches separated by isolation regions. Each trench contains multiple stacked memory cells that are electrically isolated from adjacent trenches. This segmentation allows independent processing of each trench region and enables the use of fill materials in isolation regions to reduce overall aspect ratio effects during etching operations.
2Quantity of substance
If more layers of memory cells are provided in the vertical direction to increase density, then memory cell density increases, but trench aspect ratio necessarily increases
Solution Approach 1:
The patent introduces fill materials as intermediary substances placed in isolation regions between vertical trenches. These fill materials serve as structural support and electrical isolation barriers, allowing the trenches to maintain their vertical integrity while reducing the effective aspect ratio by providing lateral support and preventing trench collapse during the stacking of multiple memory cell layers.
Solution Approach 2:
The patent employs composite structural design combining semiconductor memory cell layers with dielectric isolation layers and conductive fill materials. This composite approach creates a multi-material vertical architecture where each material serves specific functions: semiconductor layers for memory storage, dielectric layers for electrical isolation, and conductive fills for structural support and potential electrical connections, enabling high-density stacking without compromising manufacturing precision.
Data Source
AI summary
A method to ease the fabrication of high aspect ratio three dimensional memory structures for memory cells with feature sizes of 20 nm or less, or with a high number of memory layers. The present invention also provides an improved isolation between adjacent memory cells along the same or opposite sides of an active strip. The improved isolation is provided by introducing a strong dielectric barrier film between adjacent memory cells along the same side of an active strip, and by staggering memory cells of opposite sides of the active strip.